This is the BEST course I can ever find anywhere online. Very detailed, clearly explained, well outline and very comprehensive. I am Materials Science by education with little EE background. I used to work as fab process/device engineer and now I work as a Product Engineer in a major fabless company. I've been hearing about all those design terminologies (STA, PD, RTL, etc) at work but never fully understand them, and it really impedes my communications with my design and DFT partners. In the past many weeks, I have been learning both of Dr. Teman's Digital Circuits and VLSI Design classes, lecture by lecture, slide by slide, and it's super super enlightening. I wouldn't say I become anywhere close to a VLSI expert, but all these key design concepts now make perfect sense to me, and it is significantly helping my work. Thank you so much, Dr Teman, for providing such great classes online for the public. I cannot thank you enough. Also looking forward to more of your classes in the future.

Thanks ! I was unable to understand short path delay for a long time, now I finally get it.

The course is very clear and helpfull , Few uni did like this course in academia , Thank you so much Sir

Helpful lecture.....dear sir your lecture is awesome!!!!! because lectures are very neat and clean theory with beautiful example and motivation.......

excellent sir Thank you

sir for hold constraint, the line should be if jitter makes the launch clock "early" we need to subtract it from the data path delay. and not later right ?