What is wq2_rgray, wq1_rgray,rq2_wgray, rq1_wgray?

Binary to gray conversion signals

@@KarthikVippala Thank you, I understand that. But what do these prefixes wq1, rq1 and wq2,rq2 mean? Why are there two of them?

@@user-qj4ku8ov1k read and write req for each clock domain

I tested this code but some some data is corrupting

Hey Shilpa you are correct , I have seen this patent . Thanks for explaining it in detail, appreciate your efforts , good luck 👍

Namaste 🙏 Pedro palacios , thanks for your support and help inspiring words , good luck & great health 👍😊

Your welcome 🙏

Thank you so much Kun liu ,Good luck , Good Health :)

Thanks for feedback 👍

Namaste 🙏 Sowmya , thank for the support, good luck and great health 👍😊

Hey yashvir, for the reference you can check asynchronous FIFO papers in Google scholar. Be patient while reading the papers , if you have any doubts , please feel free to comment 👍

@@KarthikVippala Can u make videos on AMBA protocols..that will be very useful.Thanks

Hey yashvir , thanks for asking , I will try to make , but Amba is huge ,it will be better if you read the specification and ask the specific topic . I will help you with doubts 👍

@@KarthikVippala can u please make video on writing functionsl coverage for a moduke

Your welcome, good luck, good health 👍😊

Namaste 🙏 vinit Thanks for the support,good luck & great health 👍😊

Thank you, good luck, good health 👍😊

Improving on it 🙏

Your welcome 👍

good explaination can u explain how to implement in hdl

Namaskaram Arijit🙏, thanks for the support, good luck & great health 👍😊, do you have any topics suggestions

Thank you so much 🙏

Your welcome 🙏

Hey need video on any other topic , if I know that topic , I can do a video . Recommend some topics for video please 👍

Thank you so much Yuting Gan 👍😁. Good luck and good health brother 👊

Namaskaram Mohana Rajendran , Thanks for the support , good luck & great health :)

Namaste yeobi , thanks for the support, good luck and great health 👍😊

Thank you so much Sudeep , for such kind words, good luck, good health 👍

Namaskaram _/|\_ Massine , Thanks for the support , good luck & great health,Take care :)

Namaskaram 🙏 Jagannathan , please check out my channel playlists 👍😊

shilpa , that's longer than my video 😊 , thanks for the supportive words , you can ask any doubts here even regarding code . Good luck, good health 👍

Your welcome, good luck, good health 👍😊

@karthik, same doubt. What is 'n' here?

Namaste 🙏 Big Dawg , thanks for the support, good luck & great health 👍😊

Namaste 🙏 beautiful crafts , thanks for the support, good luck & great health 👍😊

Please do the videos on RTL integration

Namaste Manlu Piano 🙏 , thanks for the support, good luck & great health 👍😊

Thanks 😂, good luck & great health 👍😊

Thank you 🙏

To get syn rd_en , we need to do gray convertiona and pass through 2 flop synchronizer and back to binary syn rd_en. I guess.

The 2 clock delay makes the full and empty conditions pessimistic as the two points approach each other. Ingress will read full a bit earlier as information about a very recent withdrawal is delayed. Egress will read empty a bit earlier as information about a very recent deposit is delayed. If the two sides have similar throughout, a performance issue can arise as it buffets around both empty or full. This approach works best when the ingress and egress rates are sufficiently different to accommodate the delay in information between the two sides.

Your welcome 👍

Do you have any suggestions of topics for the channel 👍

You can add videos on Low power design techniques.

@@aishwaryanair7047 thanks for your suggestion , I will try to do videos on them.

Sure🙏

@@KarthikVippala thank you, can’t wait for it!

Namaskaram neelima 🙏 , thanks for the support, good luck & great health 👍😊

Your welcome

Hey abarajithan, I Will make it but need some time . Thanks for asking 👍

@@KarthikVippala Thanks you so much your, the best ! if you could explain about round robin arbiter design that would be of great help! Appreciate your efforts and your time !! thanks a lot

Hey abarajithan , I will do them, but I will ask some questions while making the video. To know what exactly you need 👍.

Hey abarajithan , edge detection means edge detection of input or not. Can you please elaborate about toggling of flop

Hey pavan thanks for asking the question, Pointer shows the position (address) where data is read or written, Address is constant , data transfer might happen into memory to correctly track the data we use pointers . Pointers a must for the design .

@@KarthikVippala got it sir 😊

Namaskaram Nitish Kumar 🙏 , thanks for support, good luck & great health 👍😊

Thanks 😊. Good luck 👍

Namaskaram 🙏 kankana , formula is for calculating range in case of non power of 2 depth , you can check fifo depth video on my channel for better understanding, Thanks for asking 😊, good luck & great health 👍.

Namaste 🙏 Sathish , pls check my channel playlist :synchronizers where I explained about it in detail, good luck & great health 👍😊

Thank you!

Thanks and welcome

Hey Tinh Lac, I understand your confusion , yes when the rdptr is passed to the wr_clk, there could be 3 to 4 clock cycles delay , with respect to rdptr in rd_clk domain and rptr value in wr_clk domain may reflect older value. This means more space is available in FIFO to write than what it is showing . When reading is stopped rdptr will catch up to the value of real rdptr. This will not effect the performance . Similarly when wrptr is passed to rd_clk domain , wrptr is 3 to 4 cycles delay compared to real time wrptr. If empty flag is generated , since we are writing there could be few data in FIFO ,when writing is completed this wrptr will catch up to the real time wrptr. There is a temporary lag in pointer value , which gets updated to correct value in several cycles. Hope this clears your confusion , if you any more doubts feel free to comment. Please do subscribe it will help me a lot 🙏

Karthik Vippala just sub

@@tinhlac1405Thank you 🙏 so much

Thank you🙏

Thank you so much 👍

Namaste Sai teja reddy, Thank you so much , Good luck & Great Health :)

Thank you son nguyen , I will improve on my voice , good luck, good health 👍

@@KarthikVippala hi Karthik, I have 1 concern: Will 2-FF syncer work correctly if write_clk is much faster than read_clk or vice versa? Any data lost?

@@sonnguyen3874 no data won't be lost , we need to take care of overflow and under read .we might get some clock cycles delay but that's fine

Namaskaram 🙏 mallikarjun, please watch cdc playlist on my channel, lint synth will update but it will take time

Thank you karthik

I have the same question!

Thank you 🙏

Thank you for your feedback and support. Can you suggest any other topic , that you need .If I know it , I will make a video on it. Please do subscribe it will help me a lot.

Division algorithm by any number. i was bit confused, can you please help me on this Thank you

@@krishnamanohar2219 can you be more specific , what is division algorithm?

Do you mean clock divided circuit?

for example 12/3 = 4. i want this algorithm how to implement in digital design

Namaskaram Sushma Kakarla , Yes you can connect output to multiple ports , Thanks for asking, Good luck & Great Health _/\_ , Take care:)

Waddr and rdaddr are not in memory and they are changed according to their own clock so gray code conversion is not required . Thanks for asking. Good luck good health 👍👍

Thank you for asking, please check video of Fifo depth consideration , link below kzfaq.info/get/bejne/ereloaelqZy9kqc.html

Do you need any video on any other topic , if I know that topic I can make a video on it.

@@KarthikVippala sure Karthik I ll let you know about it and thanks for spreading knowledge

In your toggle syn (cdc) why pulse with is increased as you said in 2 ff syn pulse can't detect. Ap you decided to use.. Toggle syn. But in toggle syn your pulse width is changed. So what you want to say.

Will get bck need to look video once

@@KarthikVippala will wait

Namaskaram Akshay🙏, gray code is used to perform proper synchronisation , in normal binary we will get false full and metastability. Good luck, great health 👍😊

Thanks🙏

Yes it's a false full

@@KarthikVippala but if grey code also can generate false full, how is it any better than binary code?

Hey shridhara , thanks for asking the question, FIFO men contain memory element ie flip-flop , registers Wr_ptr and rd_ptr contains storage elements to store the value of pointers and comparators for comparing the values and some extra logic gates. Hope this clears your doubt , if you any more I am happy to help you 👍 Please do subscribe it will help a lot . Thanks for asking

n should be such that it is greater than depth, let say depth is 520 , n will 10 as 2^10 is 1024, If depth is 9,n will 4 , 2^4 is 16. Thanks for asking, good luck.

Namaskaram 🙏 Bharathwaj , thank you , good luck, great health 👍😊

Namaskaram Ashish _/\_ , Thanks for asking , Yes extra bit also go through encoding, for depth 8 we need to use 4bit. Good Luck and Great Health , take care :)

@@KarthikVippala Thank you .

The extra bit is only used for comparison, but masked off, so that only the lower bits are used as the memory address.

Thanks Chris 🤝

@@ChrisSmith-tc4df thankyou

Hey jnaneswar thanks for asking the question , Binary pointer creates problem even if we synchronizers , I have already discussed in the video (same below) Let say we are passed 5(101) using binary counter , next value will be 6 (110) for each bit we require one flop so 3 flops and for each we have two flop synchronizers, if there is a metastability the 101 can goto 111 which is 7 and say our depth is 7 then it's a false full condition Now if we use gray pointer then here we will not get false full , metastability will change only bit or nothing . Hope this clears your doubt , you have any doubts please feel free to comment.

@@KarthikVippala got it sir, thnq very much

Hey Aditya , thanks for asking ,if it some how system enters metastability , pointers will not be changed, even if pointers are increased we will send the same values again so pointer will not be effected . Good luck, good health 👍😊

@@KarthikVippala One follow-up question, let's consider the corner case..if the pointer would have incremented it would have caused empty/full condition but, due to metastability as you pointed out the pointer will not increase and the same value will be sent. Now the comparison module will compare the read and write pointer value and since the value doesn't satisfy the empty/full criteria (although it should but it didn't due to metastability) so, the enable single will remain asserted and read/write will happen. Since we are taking about the corner case, this would mean that we are trying to write to a full FIFO or read from an empty FIFO, thus violating the criteria of FIFO design. Am I missing something here? Thanks again for your time.

Why will enable signal will be high ?

@@KarthikVippala Because one of the inputs to the and gate of enable logic is driven by empty/full condition. Since we didn't see the full/empty condition, the enable remained asserted.

@@ADITYA95KUMAR full and empty condition are dependent on wraddr and rdaddr , so I guess it won't be a problem . Can you please make question short , I am unable to concentrate for whole time😋.

Hey Balaji Adithya thanks for your support and appreciate you effort to asking the questions. Full condition is {~wraddr[4],wraddr[3:0]} == rdaddr So when wr is at 10000 and rd is at 00000 it will be a full condition . May be you have not see clearly inverter "~" due to my shabby handwriting 😁. Adding extra bit will be helpful for finding out full condition. Thank you for asking the questions , if you have more doubts , I am happy to help you.

Ok understood now! Thanks for the quick response!

So for addressing & empty/full conditions you use the binary values itself but only for sending over the data of pointer to other clock domain you use the gray code r8?

Yup u r correct 👍

@@KarthikVippala Hi Karthik, According to your formula the range of a fifo with depth 6 is from 001 to 110 ( binary ). now for checking the full condition adding extra bit may not work because if i increment the counter after the 0110 it goes to 0111 so my wraddr is 0111 and rdaddr is 0001 ( as it is the starting address ). This is my understanding please correct me if I am wrong.

Namaskaram 🙏 anil , thanks for asking, when we use 252 and 771 address , when fifo is full we rollover to 252 not zero.

@@KarthikVippala Yes I understand it doesn’t go to zero. If FIFO is full it goes to 252. If FIFO is empty it also is at 252. Then how do you decipher between full and empty?

@@Anil-yo3tx You need an extra bit in address for detecting rollover

@@JaganJohn In that case , while rolling over that extra bit will change from '0' to '1' and also MSB will change from '0' to '1' since we are rolling over from address 771 to 252. So now we have two bits change in gray code while we roll over. Can you explain that?

@@KarthikVippala Aren't we considering extra bit for roll over to decide FIFO Full and Empty condition? If yes, then there are change in two bits while rolling over. 1. MSB changing from '0' to '1'. 2. One bit change while switching from 771 to 252. Can you please explain how this would work?

Namaskaram Gauri Shankar 🙏, I too explained the same but I could have done better, thanks for giving more details , good luck & great health 👍😊

Thanks @gauri shankar singh. Now it is clear to me also.

@gauri shankar singh Can you please share the source for your reasoning if there is one .

Are you making fun , if not no problem 👍 Asynchronous counters are not synchronous sequential circuits they are asynchronous

Please find them forums , in particular there is no specific book i know which have numericals, thanks for asking, good luck and great health 👍😊