Hi Chathumini, nice to meet you and you're welcome. I'm glad you liked it. :)

Most welcome🙏😊

Happy to help!

Hi Arthur, Nice to meet you. Thank you so much for the kind words and I'm glad you liked it. Thanks, CC

Hi Shunyuan, nice to meet you. You're very welcome. Glad you like them!

Hi Ashwin, thank you so much for the feedback and I'm glad you liked it. :)

Hi SOUMEN, good to hear from you again. Thanks again and I'm glad you liked it. :)

@Mountain Eagle Glad you enjoyed it!

Hi Jeet, nice to meet you and you're very welcome. :)

Thanks for the feedback and I'm glad that helps.

Thanks for your Great suggestion! I'll do it :)

Thank you for the question. The bandwidth limited channel would cause the long tail. The CTLE will compensate for the bandwidth and extend to a high enough bandwidth such that the long tail would be reduced as low as possible.

Hi Zan, nice to meet you, and thanks for the good question. You're correct. If you have a big swing (or less loss), you might want to reduce the DC gain to get better linearity for the amplifier; otherwise, a larger DC gain should be applied for your small swing (or big channel loss) to provide a greater SNR.

@@circuitimage Thanks again for your explanation!

@@ZanZ-qi6wz You're very welcome.

Hi Nurahmed, nice to meet you and thank you for your feedback. I draw it with Visio or Inkscape, and both are similar. :)

@@circuitimage Thank you for your reply, nice to meet you too. I also use Visio but never used Inkspace before. I'll have a look at Inkscape. I liked your content a lot, keep up the good work!

Hi 正宇, Nice to meet you, and thanks for your good question. You are correct if you only looked at the absolute value 28mV (before CTLE) & 46mV (after CTLE), but the peak value of the main cursor has been increased after the CTLE (e.g., 157mV -> 319mV). Therefore, the ISI should be evaluated with the coefficient C-1, and the value is decreased after the CTLE 0.144 (46/319). Before the CTLE, the C1=0.178 (28/157)

Yes. The CTLE equalizes the swing at different frequencies.

Hi 彥全, nice to meet you. You're very welcome. Thank you for the feedback and I'm glad that helped. The digital signal is defined as only two levels: logic 1 (from the supply) and logic 0 (from the ground), but the signal level at the channel (TX output or RX input) is arbitrary (could be 0V, 0.1V, 0.2V, ... 0.7V, ..., 1V); therefore, it must be the analog signal (all possible voltage levels). I hope this simple example helps.

Thanks for the reply! Now I understand that the signal at Rx is not a clean 2 level so it is analog. But I am not quite sure why Tx ouput is also an analog signal (for NRZ), do you mean there might have some pre treatment such as pre-emphasis?

@@user-yl6cw1bt2i Hi 彥全, Thank you for the feedback and good questions. The TX output swing is adjustable. For example, someone may want to save the power by only sending the TX output swing to be 50mV or even small, which won't reach full swing to VDD & ground like the digital level does.

I understand now! many thanks!

@@user-yl6cw1bt2i Great. I'm glad that helps and you're welcome. 😀

Hi Po-Yao, Thank you so much for the good questions. The sampling clock frequency is not necessary to be the same as the data rate, it could be 50GHz, or 25GHz but multiphase clocking with half rate or quarter rate, respectively. Long story short, I'll make a video later to show how to get the half-rate or quarter-rate clocking work. Also, up to the Nyquist frequency, the most energy of the data could be, the fast slew rate still will have some small energy above the Nyquist rate, and I'll make another short video to explain that with a few simulated responses. We only compensate for the channel loss below the Nyquist frequency since we are compensating for the data response, not the clock, which could be at any clock rate as mentioned in the previous sentence. Thank you. CC😀

@@circuitimageThx for detailed explanation. So, can I have a statement with：The 100Gb/s SerDes circuit implies that the maximum data rate 100Gb/s is equal to the Nyquist frequency, which is 100GHz. But, the sampling clock might be any other frequencies depending on the circuit structure.

@@po-yaohsu2052 Hi Po-Yao, Yes, you are correct. But, the Nyquist frequency is 50GHz, which is half of the data rate 100Gbps. Thank you so much. CC

Hi 正宇, thank you for the good question. Both are the same since they are just 1-bit time ahead or behind the main cursor; therefore, the CTLE can equalize both 1st pre-cursor & post-cursor proportionally.

HI Akash, thanks for the feedback. I've uploaded the TX FFE. Feel free to let me know if you have any questions. Thanks.

@@circuitimage Thank you so much for your quick response on my comment.

Sure. Any feedback will be highly appreciated.

@@circuitimage Could you please explain transmitter driver in details if possible? Thank you.

@Akash Gupta Here you go: kzfaq.info/get/bejne/lZmmfd2gza_Ho3U.html

Hi Johnny, 非常感謝你提出這個好問題。您可以想像自己所處的位置。如果你在current bit, the next pre-cursor 1 就會干擾你current bit，如果你在next bit, 另一方面，current bit 的 pre-cursor 1 就會干擾你 previous bit.

@@circuitimage 過去有模擬如果signal經過一階RC的LPF是不會產生pre-cursor，因此在想為何經過實際的channel就會產生pre-cursor?

Hi Johnny, The RC low-pass filter is a lump element; therefore, you should not see the dispersion at the precursor. Instead, the real channel is a distributed element and the wave would disperse and spread the pulse to the precursor.

Hi shaik, nice to meet you. Yes, thank you for your good suggestions.

Hi Muhammad, Nice to meet you and you're very welcome. I'm glad you liked it. The DC gain at low frequency should be highly programmable & calibrated to the input swing. For example, if the input swing (at long-run pattern) is very huge (e.g., > 1V), you might want to decrease the swing to improve the linearity without saturating the amplifier's output swing; otherwise, the DFE cannot converge well from the SS-LMS algorithm. On the other hand, if the input swing (at long-run pattern) is little (e.g., < 50mV), you might want to increase the swing to improve the input sensitivity of the sampler (& DFE) such that SNR would be high enough. Hopefully, this explanation is what you're looking for and answers your questions. 😄

Thanks Dr. Chen for this great explanation@@circuitimage

@@muhammadkhaled0000 You're very welocme. Any time. 😀

Hi, 育瑛, you're very welcome. 😃Thank you so much for those good questions. I have comments below. Yes, you're correct. the CTLE would boost the high-frequency noise due to the high pass response; therefore, we don't put too much bandwidth than what it needs in the CTLE design. In addition, the passive CTLE would have a less SNR than the active CTLE if the active CTLE burns reasonable power.😀 Usually, we care about the 3dB bandwidth (not the whole flat response bandwidth), as long as the 3dB BW is ~5GHz, the signal's frequency < 5GHz should be okay and good enough for 10Gbps. 😄

@@circuitimage Hi Dr.Cheng, thanks for your reply! 1. As you mentioned, we don't put too much BW in the CTLE design. In this case, it won't contain too much high frequency in CTLE, so we can get less noise, right? And I think we may not say CTLE can not boost high frequency, shall we say CTLE will decrease the power in low frequency to compensate the loss of high frequency through channel. 2. The CTLE you mentioned in the video is active CTLE since it has higher SNR, but how could we distingush passive and active CTLE? 3. I'm wondering that if the IP is like USB4, the data rate is about 20Gbps, then could it still work Additional inquiry, 4. Can we improve the CTLE's filter ability by adjusting the AC and DC gain since in the CTLE design the resistor and capacitor are parallel, but I'm not sure this is correct or not. please correct me if I'm wrong. I really appreciated that, thank you again

@@user-kt5rx6hf9b Hi, 育瑛, you're very welcome. Again, thank you so much for those good questions. I have additional comments below.1. As you mentioned, we don't put too much BW in the CTLE design. In this case, it won't contain too much high frequency in CTLE, so we can get less noise, right? And I think we may not say CTLE can not boost high frequency, shall we say CTLE will decrease the power in low frequency to compensate the loss of high frequency through channel.[CC] Yes. 2. The CTLE you mentioned in the video is active CTLE since it has higher SNR, but how could we distingush passive and active CTLE?[CC] Please check this one: kzfaq.info/get/bejne/gNl5daSiyb_Lpok.html 3. I'm wondering that if the IP is like USB4, the data rate is about 20Gbps, then could it still work[CC] No, and I'll make another video to show how it works. Additional inquiry,4. Can we improve the CTLE's filter ability by adjusting the AC and DC gain since in the CTLE design the resistor and capacitor are parallel, but I'm not sure this is correct or not.[CC] Yes, and I'll make another video to show how it works.

@@circuitimage Thanks for your reply, I'm looking forward to watching the new video, thanks agian.

It is ready. Why Active CTLE in a high-speed SerDes? kzfaq.info/get/bejne/gNl5daSiyb_Lpok.html

Hi Frank, thank you so much.

Thank you for your interest. 😊

@@circuitimage I mean kindly share the slides to your lectures.