Thanks for the feedback and please share w/ someone may benefit from it.

Hi Po-Yao, nice to meet you. I'm glad you learned a lot. Thank you for your feedback and hopefully, we could meet one day in Taiwan. 😀😀😀

Thank you so much for your good questions. Your understanding is correct and we can.

@@circuitimage Thanks for your reply

You are very welcome 🤗

Hi boon, nice to meet you and thank you for your feedback. I'm glad that helped. 😊

Hi Hanyue, Nice to meet you. Thank you so much for the good question. The example I've shown here is a half-rate DFE topology; therefore, the rising edge of the clock would sample the 2 levels eye diagram while the 4 different levels eye diagram was settled in the summing nodes. Hopefully, this helps your understanding. Thanks again.

Thanks for the feedback and please share w/ someone may benefit from it.

Hi Minh, Nice to meet you, and thank you for your great question. The DFE would not be immune to noise & crosstalk, but at least the DFE would not amplify it. For those noise & crosstalk are mostly high-frequency content, and the CTLE would amplify it (at the frequency greater than the Nyquist rate) and de-emphasize the DC content and reduce the SNR. So, the DFE would be less vulnerable to noise & crosstalk than the CTLE.

@@circuitimage thanks for clarifying. Keep up the great content. 👍🏻

@@MinhPham-je1gt Sure. Thanks again for your great feedback.

@@MinhPham-je1gt Sure. Will do and I hope to receive more great feedback from you :)

@Hrachya Khachatryan Thanks for the feedback and I'm glad you liked it. I have comments below. 1) No, it's like an IIR since the feedback tap 2) Both TXFFE & DFE are discrete-time, but both TXFFE & CTLE will amplify the noise, but the DFE wouldn't; therefore, the similarity is still different in terms of properties :)

@@circuitimage Thank you )))

@@hrachya_khachatryan You're very welcome :)

Thanks for the feedback and good question. You could apply a sliding tap or separate summing amplifier to reduce the loading for the 1st tap at a high-speed SerDes. Let me know if that's not clear to you and I could make another video to emphasize what I meant.

@@circuitimage Yes that would be something interesting to learn about(regarding the tricks to reduce capacitive loading on the summing node)! Look forward to it!

@Zheng Lai :) Here you go: kzfaq.info/get/bejne/eMB8iatenbCqqac.html

Thanks for the feedback and good question. The case study of those reflections was just an example of 3UI, 6UI, and so on, which might not be in other cases. The reflections may be from the discontinuities in the packages, vias, connectors, etc. So, every link could have different reflections in time so as the response in the frequency domain. Lastly, not the bumpy response creates a reflected waveform. The discontinuities at the interface would create a reflected waveform and the bumpy response was just the frequency response due to the discontinuities.

@顏擇敏 Thanks for the good question. The DFE is decision feedback to cancel the previous bit (symbol); therefore, that only canceled the previous bit's post-cursor. Technically, the DFE cannot cancel the previous bit's pre-cursor.

Hi Jimmy, nice to meet you and thank you so much for the excellent question. I'll make the compliance test video for the "PCIe" & "10GKR" or others to elaborate on that. :)

@vars008rcb nice to meet you. Thanks and I'm glad you liked it. The FFE would decrease the DC swing and boot the high frequency (most noise content), so the high-frequency noise is equivalently amplified.

@@circuitimage Thanks for the quick response. It makes sense!

@@vars008rcb You're very welcome :)

@@vars008rcb Thanks for confirming my mental model of the FFE image as well. :)

Hi Zan, nice to meet you and I'm glad you like my videos. Thank you so much for the excellent questions. Please be advised that both the eye width (EW) and eye height (EH) are correlated; therefore, if EH is improved, the EW should be improved. But for DFE, there's a subtlety since that would require feedback (FB) timing or settling time requirement and most of the data DFEs cannot FB fast enough, so that's not improving the EW effectively. I can show other edge DFEs images later, and that would help the EW effectively.

@@circuitimage Thank you teacher! another question. If I see the eye width is horizontally shift left / right side, Which parameter I should check?

@@ZanZ-qi6wz Thank you so much for the good questions. If the eye width was shifted, you could check if the TXFFE or CTLE did not cancel the pre-cursor well enough. Another possibility is the DFE's settling time takes too long, even though it meets the 1UI timing. :)

@@circuitimage Thank you very much for your explanation again! Very helpful!

​@@ZanZ-qi6wz You are very welcome. :)

The number of taps means how many Tbit (or UI) you can cancel the length of the ISI. For example, if you only have 2 taps DFE, you can only cancel the 1st & 2nd post-cursor by the 1st tap & 2nd tap feedback summing signalling to cancel the previous ISI; therefore, you cannot cancel the previous 10 UI's ISI, for example.

@@circuitimage Understood. Is there an article or link that explains how to configure taps for DFE in detail? Also, do you have an email ID for further question?