sorry I mean usually in schematics there is at most like one clock buffer

Hi Eric, thank you so much for providing this insight. I agree, but the more clock buffer, the more timing uncertainty is, which may be even very difficult to analyze. So, I don't think we need to risk the negative setup time by lots of clock buffer chains. :)

@@ericsu5909 Yeah, I see and make sense, which depends on how you designed it. If we only look at flops without buffer, then that could be more obvious. :)