Hi Hanyue, nice to meet you. SerDes PHY includes a Physical Media Attachment (PMA) hard macro and Physical Coding Sub-layer (PCS).

想請教 李大 ，您認識的這位學長 是叫什麼名字，是教授還是在業界上班的高手，看了一系列的分享課程很厲害，想知道這位大大是誰。謝謝您

Thanks for the feedback. I'm glad you like it. Will do more for you :)

You're welcome.

Hi Sai, thank you so much for the feedback. I have comments below in line w/ [CC]. 1. what is the importance of dots over inductors? [CC] Good question, the mutual inductance should be added (not canceled) to reduce the area.2. How do we choose the cpar? [CC] Cpar would be part of the ESD cap, which depends on the specification of the protection strength.3. Is the capacitance added to cpar intentionally in some cases?[CC] Cpar would be part of the ESD cap, which was added intentionally for protection.4. how to make a T coil in layout? Is it just achieved by placing inductors next to each other? How far should the two inductors be? [CC] Good question, you could just place inductors next to each other, but the coupling would be limited and may consume more area. Our experience would be as close as possible to save the area under a customized routing. 5. could you please point to a research paper that uses a T coil to improve the matching?[CC] I worked with Professor Razavi about the T-coil and he had a good paper shown below. www.seas.ucla.edu/brweb/papers/Journals/BRFall15TCoil.pdf 😀

Thanks for the good question. I think the square should be good enough since the Q of the T-coil is not as critical as the coils in the LC-VCO. Both shapes of the octagon or circle would be a layout constraint, which might not be necessary.

Hi 育瑛, thank you so much for the good questions and I have comments below. 1. As your mention, we can add a T-coil close to RX in the transmission line to reduce the return loss since T-coil is L+C, it's just like the LC in the transmission line, but if the R termination has perfect impedance match, it also can cancel the reflection, so that we don't need to put T-coil. [CC] Sometimes, the single inductor would be good enough, not necessarily to have the T-coil. 2. If we need to add the T-coil in the transmission line, then how to decide the inductance and capacitance. [CC] That's not easy to decide and it depends on the ESD cap or size, which may correlate with the bridge capacitance and two inductance values. The ballpark could be 0.5/SQRT(LC). 3. This is just my wondering, I think the L and C are just the imagination in the transmission line, we don't really put the components(L and C) there right, but for the T-coil, we really put L and C there. Kindly please correct me if I'm wrong. Thanks for your help again. [CC] That's correct.

@@circuitimage I see, thank you so much, it's really helpful to learn knowledge from your video, thanks agian.

@@user-kt5rx6hf9b Hi 育瑛, thank you so much for the good feedback and I'm so happy I can help you.

Hi Jeremy, thank you for the excellent question. You are correct. If you connected the RX input to the 2Rterm directly, the BW would be wider. But, the SNR may not be good since the BW is more than what you needed. Any unwanted high-frequency noise, crosstalk, reflection, etc, would not filter out properly. Therefore, for the data rate > 100Gbps, your suggestion is needed since the BW might not be wide enough. Again, the BW of T-coil design would depend on your application and I may talk about those tradeoffs in detail in another video.

@@circuitimage Thank you

​@@jeremywang6785 You're very welcome.😄

Hi Po-Yao, thank you for the good questions. Yes, you're correct about 1 & 2. To be clear, the Z0 (50 Ohm) is the single-ended impedance. 😄

Hi Zhongpeng, nice to meet you and thank you for your good questions. My understanding is the DC does not matter since the coding may provide the DC balance; therefore, the minimum frequencies for the return loss would not be DC. Could you please let me know which protocol or standard is defined at DC? My understanding is 100MHz for OIF-CEII or 50MHz for PCIe, but I could be wrong. 🙂 In addition, the 10dB or 8dB may provide the reflected power to the transmitted power to be ballpark 10% to 15%, which would be reasonably engineering good enough judgment. 😊

@@circuitimage Hi, Chen, usually, return loss mask specifies the maximum dc return loss. I saw a paper published on JSSC demonstrating a TX chip with -25dB return loss at dc. DC means 0 Hz. But with no further explanations. I guess that a lower return loss at dc makes it easier to meet the overall return loss mask requirements across frequency range. I am trying to devise new circuits with relatively high return loss at dc but sitll within the limit（-15dB or so）. My understanding is that TX dc return loss translates to negligible swing reduction at the RX inputs through higher insertion loss. Therefore, I believe that return loss dc is important just because a lower dc return loss means more headroom at high frequencies for a mask. Do you agree？Again, thank you for your patience and professional advises！

@@kunchen4871 Thank you so much for your great feedback. I agree with you that having a great return loss at DC (0 Hz) would be a starting point to help you meet the overall return loss mask requirements across the frequency range easily. Usually, the return loss would be getting worse at high frequencies and the lowest at the DC. But there's a caveat you should be very careful. In order to meet the good return loss (RL) at DC (0 Hz), you could add too many switch (NMOS, PMOS, or both) legs to reduce the switch device & parasitic capacitance. Those capacitances would degrade the high-frequency RL quickly and usually, that's happening when we could get a very good DC RL, but cannot meet the high-frequency RL. Then we might add the coils to extend the impedance at high frequency, but the coils might add too much DC resistance (if not designed properly) and make them less signal-to-noise ratio due to DC RL degrading unexpectedly. 😃

@@kunchen4871 Your understanding is correct. Relaxing the termination for a low power purpose is practical in the industry, but we still need to keep good timing at the RX side to make sure the distorted eye won't degrade the BER too much. :)

@@circuitimage Thank you very much.

Hi Feifei, nice to meet you. We use Keysight's ADS momentum simulation. Thank you so much for your good question.

Hi Raj, nice to meet you and thank you for the excellent question. People applied both ways. If you connected the RX input to the 2Rterm directly, the BW would be wider and may have more peaking. Also, the SNR may not be good since the BW is more than what you needed. Any unwanted high-frequency noise, crosstalk, reflection, etc, would not filter out properly. Therefore, that might applied for the data rate > 100Gbps. So, if the BW is just good enough on your application, connecting RX at the midpoint of the t-coil would be better. 😄

Thanks for the amazing answer. Could you please explain why connecting at the Rterm is wideband? Also, i learned from the basic theory that we shouldn't load the Termination node as the cap will be sensitivity where as the center tap node can swallow as much cap as it could. This is exactly what I have seen from the publications, all 224Gb/s applications connecting at the termination.

@@Aadhyacedt You're correct. The L is connected to the C of the Rterm directly could extend the BW through the LC peaking; therefore, for 224Gbps, I think people may try to make more C-L-C-L-C like pi coil to make it more BW like a T-line. Also, the center tap node needs to be sized properly; therefore, the parasitic from the terimations could work (if Cpar of the Rterm is not too much) or might not work (if Cpar of the Rterm is too much).😀

The T-coil's calculated parameters would be L1, L2 & CB. You could apply a simple impedance equation to drive what you need. ZL=sL & ZC=1/(sC). Then decide how to decide the values of L1, L2 & CB.