What are the tiers?

SABCDEF

True professional

I second this

Yeah, pretty much. The most complex soloutions had to be found to make stuff faster

If anything it's TLDR: The article is wrong cause the author doesn't know what they are talking about.

@@julkiewicz Did you read the article? It was about how ancient rarely used instructions, and the sheer bulk of instructions take up valuable space and increase complexity. The only times "fast" was mentioned was them saying speed was their only priority.

​@@bits360wastakenBut modern chip designers also know that, and they only allocated the bare minimum amount of die space and power to those obsolete instructions. Deleting those instructions won't yield any visible change.

I think amds 3d VRAM shows that

Die is just inherited from the manufacturing process of chopping something into many smaller pieces or "dicing", a large piece of silicon get diced, so the smaller pieces of silicon become die, there is no big mystery. Same as dicing an onion.

I think it is called die, because you dice a wafer into many die, not because of the printing "pattern" die.

I think the “problem” is more complex these days than raw performance. When it comes to making portable work stations, raw performance is a factor, but it is not the only factor. I think ARM is winning because a balance between performance and performance per watt. The smaller instruction set allows more efficiency gains, and thanks to modern 21st century programming toolchains and compilers, the disadvantages of a smaller instruction set is not nearly as much of a cost.

​@@excitedbox5705 Or maybe because when you print the dies you are casting a metaphorical die (old English singular for dice) that determines how many individual units (cores) of that die are error-free at the targeted frequency? I'm probably overthinking it.

Having thousands of rarely used instructions on die, multiplied by the number of cores (dozens today) can be wasteful. There are good uses like your AES example and bad use cases. The rare instructions can be avoided by the compilers, replaced with decent equivalents. Decoding consumes transistors and power, termal throttling is a fact. Where is die coming from? Remember the times when circuits were printed on a board with the traces covered with paint, then the board is treated with iron chloride FeCl3 to remove non-covered copper (etching)? Now it is done with EUV light, but it started with die 50-60 years ago.

nah, it uses twice the space, it's more expensive, and you still need to move the clothes from washer to dryer yourself besides, who's doing more than one load of laundry a day?

​@@squishy-tomato is that a single or someone in a two-person houshold talking?

​@@XDarkGreyXtwo person? Have kids...

They're pretty great since you don't have to bother moving the clothes half way through. So you can throw a load in before bed or whenever. The main thing is that the drum for a dryer is about twice as big as a washer for a given capacity. So you can easily add too many clothes for it to dry well.

@@XDarkGreyX doesn't matter, doing one load a day is not a big deal

Chat went on about the transfer between the machines, which I noticed too but... should he have addressed that when it comes to the hardware pipeline?

@@XDarkGreyX The transfer would basically be instant, it's just a bunch of clocked latches that separate each stage

The laundry machine analogy is like the standard go-to for explaining pipelining. The buffet analogy also works.

Learning how to teach is a skill which has nothing to do with the knowledge you're teaching.

@@BrunodeSouzaLino I feel as if millions of tenured researchers with teaching loads cried out, then were suddenly silenced. Perfect way to sum it up. If only the vast majority of people that taught realized it was so much more than verbally repeating something to a room full of 20 somethings.

Him and Jon Blow are my top ones.

You might also search for "The Intel 80386, part 1: Introduction Raymond Chen" and read part 1 to n.

They actually make you study x86 ASM at college these days? Back when I was at university they did cover ASM for a simple microprocessor (I forget which). But not the x86 architecture. That was in the late 1990s. ASM is irrelevant for most software developers these days. Compilers will typically produce more optimised machine code than you can do manually with ASM. Unless you really know what you are doing and there is a specific case that the compiler does badly at (or can't do). ASM is useful to teach you the inner workings of a CPU though.

@@RetroPcCupboard Knowing assembler helps you understand what the compiler produces and how high-level languages work. I think this is very valuable knowledge, it's like Latin for languages.

@OpenGL4ever Sure. If you are interested in that. I think most developers these days don't really care how the compiler works or even what the inner workings of a CPU are. I actually find it fascinating. Despite the fact I have been a software dev for 25 years I am only now learning x86 assembly. I have an old Pentium MMX PC that I am using for the purpose. I realise that I could do it on a Modern PC. But I feel that a slower PC makes more sense for seeing the impact of ASM vs older compilers.

@@RetroPcCupboard man, someone study computer engineering, how can we not study x86 asm if we study how to develop said processors? =)

Congrats

My first paid for programming job was in 1979, but I wrote my first program in Algol on paper tape in 1976. Really like this guy because he speaks my language, and calls out the downsides and very real practical impact of today's fashionable sacred cow practices.

ty for your service

Oh cool, like honestly. What were you programming? How was the debugging process without fancy IDEs? What was it like to describe your job to other people? Could you elaborate more if you don't mind how different it was compared to today's way of software development?

as old as turbo C ! (anyone know a good decompiler for dos ?)

I'm not dyslexic, but I'd like to think I am to justify me reading very little

Man, I'm not dyslexic but I'm still the slowest reader I've ever met.

If it helps, you can think of it as "pipelining". If you were just reading it yourself, you would be reading it yourself. But since you are hearing him read it, you can go do other task. Cue multi-threading. (Or get entertainment out of it while still learning)

I can read fast but just as in school I may need to read a sentence 10 times even at low speed to even just barely get it.

@@ark_knight lmaoooo true

I think it only occurs to us when we've done assembly programming, or bit-banging level C programming.

@@andrewdunbar828or speak German, numerals from 21 to 99 are little-endian there. Or when we add/subtract/multiply on paper, somehow it’s easier to do little-endian.

@@YaroslavFedevych Ja ich weiss es! In English numbers are big endian and can make writing functions that do things like decimal conversion, ASCII conversion, adding thousands separators a bit unintuitive or at least more tricky. I started assembly on the Z80 which was little endian but lost the feel for it so much after moving to the big endian m68k that little endian never felt natural again.

@@YaroslavFedevych gimme 99 of them luftballons, amirite? In Norway we actually can pronounce the numbers 21-99 in both big endian and litte endian. The little endian variant is more common with older people, it's unfortunately dying out.

Yeah, even I understood, I was a bit surprised by the lack of enthusiasm.

More and more people use hammers but fewer and fewer know how do build or at least understand them? Applies to countless fields, but would that be a valid metaphor?

@@XDarkGreyX Yeah... That metaphor sounds totally reasonable to me! 👍🏼 Particularly in this industry.

XD the mirrored Mercy from upcoming season would fit great.

While riding on a fake horse ;)

​@@technomancer75 should be cow he is riding on. He owned a cow once, or does own them still.

Damn right we just understood it so easily with that explanation

ford's assembly line could have served better

Yeah, I finally have a way to describe the concept to other people. Very helpful.

The fast-food drive thru is a pretty good one!

Yup! Using that from now on!

Yeah people blaming intel / AMD for "bloated" x86 and "tech debt" as if this decision was not made solely to please the customers is pretty incorrect

I had this thought too. Intel tried to fix these issues in Itanium. It's now nicknamed i-tanic because no one wanted to recompile their code to run on Itanium. I'm not at all a fan of Intel, having worked there for 2 years back in college many moons ago, but you can't soley blame them for x86 legacy.

@@AlecThilenius as I recall, Itanium never achieved the supposed performance gains, even if you DID recompile your code. In the Linux world, Debian alone supports 4 different CPUs. x86, MIPS, Arm, and PowerPC. Re-compiling isn't really a problem. I believe Itanium was supported. The servers themselves were freaking EXPENSIVE. I've honestly never seen one, used on, or worked anywhere that had one.

X86s will probably be the actual solution for Intel and AMD. It can run older programs just fine, no problems at all with any 64 bit x86 code and will just strip out the unused part. Intel published it and I hope they move forward with the idea.

@@stevesetheryou underestimate how much technical debt for legacy dos and Windows 95 software run on modern business. No compiling Deb files for PowerPC or arm won’t help run accountings old Oracle macros written vb 5 back in 1998 in Excel only.

Then I have a question. I've also heard that Intel would like to throw out some things. But if a CPU has, say, 8 cores, would it be possible to just throw those things away at 7 cores and keep them at just one core? Especially the old stuff that was used in the DOS era was never written for multicore CPUs anyway. This old software would therefore only need this one full-fledged core.

@@OpenGL4ever I had a similar thought. If you suddenly take away the x87 FP stack, what software is suddenly going to break without being re-compiled? It might make a lot more sense to just de-emphasize these old instructions, and make them work, but not as performant.

​@@stevesether I don't know what Intel's proposed solution is, but I imagine they have a way to hook those instructions at execution time and deal with them. Since they're very old instructions, they have the benefit of only occurring in very old code. Sure, you could use a ridiculously complex decoder to convert them, but you could also do something crazy like raise a flag to the operating system and flag the code to be decompiled and rebuilt into equivalent compatible instructions by an OS process, and link it back into the original executable. The first run might be slow, but the second time would be real fast.

yah, unfortunately the article author and even the commentators have reasons to not really be.. honest so to speak.

makes sense, these are very old and i don't believe they ever been used, since the pentium era, if ever. the x86 compatibility goes a long way but i guess it's on the safe side, mmx/sse were being used instead. there are also some other legacy stuff that can be removed safely. as for the renaming, isn't intel already using, in lack of a better term, indexed locations for the registers? maybe you can shed some light here because i really don't understand exactly what they do, if that holds any truth.

He looks like he was born in 1988 at most. He must have been programming at the age of 7! No wonder he is a genius

Wait until you get a load of us early 70s Gen-Xers who learned to program assembly in the early 80s, and went on to program things like Battlefield, Minecraft, Skype, etc. Oh, and Linux.

I thought the definition of ancient was knowing of EBCDIC and having an IBM 370 gold card within arm's reach.

Unless you're solving math problems using vacuum tubes, I'm not sure what exactly you all are defining "ancient" as.

@@TheVoiceofTheProphetElizer Well I guess we could go back to where a program's bug is a moth caught in a relay ...

I was more impressed he 2as writing backwards

@@jewlouds Nah, the camera is flipped horizontally

The scroll-up got me

didn't find anything that's authoritative on this, but I did find a few results referring to the process of cutting up a larger item into square pieces being "dicing". the results of that are "dice". an individual item is a "die", and found results saying that was the etymology for integrated circuit dies. CPUs aren't stamped/casted/extruded, and never have been, which is why I am not sure the linked wikipedia die concept applies. But I can't fully argue either way. What I can agree with is it is related to the manufacturing process. We can be pretty sure of that.

@@blarghblargh the specific use of die I mean from the article is a stamping die. It's basically a matching set of "knives" with a complex geometry. The dies are pressed together with the material in between, and while I doubt that's how silicon chips are cut these days I can believe that's how it would've been done in earlier days.

@@nahkh1 Integrated circuits are batch manufactured in a grid pattern on a wafer of (most commonly) pure crystalline silicon. The individual product pieces are separated from the wafer ("singulated" or "diced") using a saw, which converts the wafer into a large number of identical small parts collectively called "dies" or sometimes "dice" (older usage) and one of these is called a "die," and this term in a semiconductor industry context always refers to the product and not the tool. There are a few other rarely used singulation techniques other than a saw, like laser cutters, waterjet cutters, even particle beams that can cleave the wafer by precisely imparting millions of crystal defects in a line. As far as I know we never used stamping die-cut (where "die" means tool, not the product) techniques though; silicon crystal is quite hard and brittle, and the wafers chip and shatter more resembling thin discs of glass than thin discs of metal. Nonetheless, I'm sure the terms share a common history. There are other contexts too, where die and dice refer to the product and not the tool that made them - for example, playing dice.

What made you switch to Linux that early?

@@PixelThornnot op but similarly old, when win95 came out, I felt it “hid” the true OS and hated it. When I heard about Linux in 99/2000, I was an instant convert.

@@PixelThorn Windows 95

@@idhindsight Hiding isn't bad. It's just a diffrent client use case. That helped Microsoft gain the popularity it has today.

@@darekmistrz4364 ehh I didn’t say it was objectively bad. It sure as hell isn’t for me (and most developers)

That was a pretty useful explanation.

I read they use 70~ bit registers to store flags + GPRs.

You are right. The only complaints about CISC in x86 are the variable length of the instructions that makes decoding a more complex and also the rarely used instructions carried over the decades.

Are you sure about your last point? With ARM you can start decoding instructions in advance, because all of them are 4 bytes each, so you don't need to wait for decoding to get the address of the next one. With x86, on the opposite side such a dependency of variable length doesn't allow for it. I think it can outweigh the increased pure count of simple instructions, especially if there is no code bloat and hardware instruction memory prefetching does its job well.

@@mitrus4 - Program memory is loaded from RAM into processor caches, which on Intel chips are divided into interchangeable 64-byte cache lines. The cpu instruction decoder has no need to calculate the RAM address of the next instruction, it relies on the program counter to automatically keep its local instruction cache full. If that instruction cache ever underflows, the instruction decoder will have to wait until the cache is refilled from RAM. However, cpu execution units and data load/store units can continue to process previously decoded instruction micro-ops, which proceeds speculatively in parallel with instruction decoding. In practice, it is far more common for execution to stall due to logical or algorithmic dependencies than for speculative execution to outrun instruction decoding. With ARM cpu's, each machine code instruction is four bytes long. On Intel cpu's, the most common instructions take just one byte, though complex instructions can be up to fifteen bytes long. On average, Intel machine code tends to be about half the size of ARM code.

I also wanted to say that I forget the laundry or that you need a specific person to sit next to the washer not to forget to move it from washer to dryer

Yeah chuck a good mobile Ryzen processor to linux instead and the difference i heard is night and day with battery life improvements in the 10's of %

Don't disagree but that 5/10% on something that could be delegated to compilers in a post-moore's law world is more relevant than you might think

Modern ARM and x86 and even RISC-V ISAs are pretty much all nearly identical. They can all do the same things and the notion that ARM is a "less complex" architecture because "ARM is RISC and x86 is CISC" should only be made fun of. However we are at the point when we have to scrape the bottom of the barrel for miniscule gains.

Yeah, I don't want the main RAM as a permanent, unchangeable fixture of my computer the way Apple does things now. Now is true that one could produce a lower transistor count x86 if stripped out all of its legacy stuff and only implemented the instructions used by modern software and operating systems. That would be an interesting project (and am suggesting cleaving more than just the CPU coming up into 8086 real mode). After all, any modern CPU per its performance can more than adequately emulate vintage CPUs of the '70s, '80s, up to mid 90s - for those that want to play their fav retro games. Retro computer emulators on ARM - like the Pi - prove this every day. So x86 doesn't need the transistor real estate that is dedicated to supporting stuff that are vestiges from 40 years ago. Git rid of that fat to lower the power draw. And aren't there too many redundant SIMD instruction sets - why not trim that down to what is only in vogue in, say, last decade?

@@TheSulross especially with EFI being so commonplace, a lineup of "stripped down" x86 parts could maybe be viable... but then again they have hundreds of engineers wracking their brains all day long about performance and power efficiency improvements so it's not like they haven't thought of the same ideas as us smoothbrains have (and there's probably reasons they concluded they're stupid).

Huh, really interesting that you are here. Kudos. *clap clap*

most of programming are techniques only an engineer truly needs to do. but computer science is a beautiful subset of math that anyone can appreciate. as an arborist you are likely implementing the same optimization techniques that CPUs use without thinking about them, multitasking, task overlap, task reordering, pipelining, etc. it’s just a definitive way to think about the world

@@loo_9 Like i said, I've been building side projects for a while. One of them is a nifty nodejs and nedb tree notes app that lets me keep track of progress and search for any key words or time intervals. Now I want to get some charts going to show trends. I have almost 10 years of data, that I've been gathering. Including daily weather conditions. So... ya. I tree surgean by day, and code at night. And the best part is, I have no deadlines, no HR directors, no tiresome teammates... ;-)

> But it's good to know how the things in your life actually work. This. This is the reason I enjoy computing, from both a hardware and software perspective. Yes, the tech is cool, but what I truly love is understanding what the heck these magic boxes of lightning and sand actually _do._

As an arborist, you're officially a HACKER :)

nasa loves those coc pc on chip ecc ram [x3 mCHINES IN CVASE SUBSPACE TREKKING BIT FLIP DISAGREEEMENT]

This sounds like medieval torture of computers. I wasn't aware someone could even program in machine code. Big copium.

You'd be going back to itanium and ps3 cell processor level if you did that, haha

And Modified Von Neumann means they have separate caches.

To me this was taught with emphasis on different busses: instruction bus and data bus can be accessed simutaniously, and can have different widths. For example 14-bit PIC controllers have 14-bit instruction bus, but 8-bit databus. Any modern microcontroller needs an ability to write instructions while running and execute them later: I don’t want to rewrite the Rom of my laptop everytime I install something. And the kernel needs some way to give userspace code access to the CPU (the alternative would be virtualisation, I think). Either way the relevant consepts of privilege are so far removed from the hardware that the distinction between Von Neuman and Harvard architectures isn’t as meaningful as their orginal definitions.

The idea of von Neumann's idea is not about address spaces, but about the representation of the program: if it's represented as data, we need no extra mechanism to handle it (load, save, execute). The executor unit (CPU) already should access memory, loading and storing data from/to, so if we represent program as data, it's not a big deal, we can use common mechanisms for it. I don't know how computers looked before this idea, AFAIK, the programming was done by re-wiring the whole computer physically for the specific task (aka. program). Storing program in memory is a brutally significant improvement: need longer program? just add memory; bug in program? just modify some bytes - etc.

There's also Mill architecture

@ern0plus4 in the really old days, when computer where mostly mechanical devices like the enigma machine, you had mechanisms for "instructions" and another medium like paper cards for "data". When they started moving from mechanical to electrical they still handled instructions differently from data. It wasn't until the first silicon transistors that you made and handled data on the same material. Today it's a bit odd as on chiplets we go back to using different processes on the same wafer, so we somehow got different materials again. But basically any CPU today doesn't distinguish between code and data. But it might come back if people really do care about security. Harvard architectures are far more robust by design against injection attacks.

And then you need to remember that all that computer is doing is juggling memory: from disk to ram, from ram to L3 cache, from L3 to L2, from L2 to L1, from L1 to CPU and all the way back to disk.

fireship?

You can't go that far because the halting problem gets in the way. By the last iteration, Itanium was a bog-standard architecture that basically ignored the whole VLIW aspect entirely.

Just encode the processor control lines directly! Pay no attention to how you actually read the instructions...

@@SimonBuchanNz the ISAs don’t just vary in syntax, but in semantics and in guarantees. These guarantees must be fulfilled.

Conroe

its probably just a massive piece of glass that can move up or down with the help of motors

@@c0dy42 I believe it's a sheet of plastic that's rolled up on the top and bottom.

I take his course and he uses it all the time. I'm not exactly sure how he does it but probably a foot pedal. We saw the full height of the board in this video, so he has to wipe it when he needs to use more space than this.

@@APaleDot I thought that at first as well. but I think that we would be able to see that, because then there would have to be a big piece of acryl or Glas behind it, so he has a solid surface to write on.

Its nice that LE still ends up being useful when things are scaled up

CEPT W MORE UV LIght less heavy hamnmer head bangers:)

GameBoy?

@@X.A.N.A.. No, but a few arcade machines. The GameBoy uses a Rico clone of a Zilog Z80, which is related to the 8008, but not compatible, just as the 8086 is related to the 8008, but not compatible. The book called "Nailing Jelly to a Tree" is a good Z80 starting point.

I was looking for this comment! The special purpose uses if the registers and limited addressing modes are the 8080 legacy issue. Compared to the Motorola 68000 series consistent registers and addressing modes makes programming the 68K a dream compared to Intel. Sadly they couldn't keep up in performance and lost out to x86.

What are other 4?

@@darekmistrz4364 lol idk.

This is a valid concern, but on the positive side, we survived the UEFI transition, and I'd argue it mattered more to the IBM PC ecosystem than the ISA

@@Bokto1 It's about the complete package indeed. And UEFI was probably only "survivable" because it had to compete with the ol good MBR in terms of not being a locked down hell.

While not knowing that much about the topic, I feel the main reason installing something else on a phone or console is the hardware and the UEFI (or whatever tf they use on those) are meant to be sold as one single piece. I don't think that has a chance of coming to PC and servers as both have to be customizable.

@@truegemuese It would be a bit harder to come up with a system that allows it to be locked down to the OS and still allow you to change the hardware, but it's sadly not impossible.

x86 is objectively bad both for hardware and for designers/users. x86 decode takes too much energy. 12 ALU instructions make up 89% of all x86 code. Despite this, average x86 instruction length is 4.25 bytes which is LONGER than pretty much any RISC ISA you can name. A study looking at Haswell a few years ago showed that when processing ALU instructions (remember, just 12 of those are 89% of all code), the decoder used over 20% of total core power. ARM's A715 went from 4 to 5 decoders while reducing decoder size by 75% simply by removing ARM32 support and ARM32 is still WAY easier to decode than x86. x86 has memory ordering that is far stricter than necessary which disallows optimizations. x86 instructions are bloated with all kinds of weird exceptions. A register is still special as the accumulator. A+D are used for MUL/DIV results (except 8-bit which use just A). 2-register only means you have extra MOV when you don't want to overwrite a register. 16 GPRs (more like 12) also bloats instructions. Then there's really weird stuff like the parity flag that definitely doesn't do what you'd expect with larger values. Most important though are the designer and dev costs. The ISA bloat flows throughout the entire chip design. This makes component design and testing take way longer and cost way more. If x86 were the only option, we wouldn't be seeing the startups that we see with RISC-V. Likewise, the complexity of x86 means that even most low-level programmers don't understand it past maybe a handful of instructions and the idea of actually understanding the binary format is basically inconceivable. Something like RISC-V is understandable to these programmers. This becomes even more important and obvious with SIMD where compilers suck so much. x86 SIMD is a minefield of some 17 different extensions (if you count AVX-512 as just one extension) and none of them are easy to use. In contrast, RISC-V vectors can be understood by normal coders which means they will be much more willing to use those vectors which should result in faster code for consumers. I'd also note that most universities have switched or are switching to teach RISC-V, so there's reams of programmers entering the market who already know the ISA basics (meanwhile, there's no hope that any school is going to fit x86 into undergrad coursework).

@@mrbigberd x86 is backwards compatable since 1981. point invalid.

​@@bionicseaserpentif your point is that changing x86 would break compatibility then yeah, I don't think anybody would deny that. But the rising adoption of ARM/RISCV does the same anyway (as does changing to newer OS or hardware for that matter).

​@@mrbigberd Firstly, thankyou for your response - it makes me happy that someone took the time to read my words, even if we disagree. As I expressed, everything you're saying I could have been saying myself ten years ago, I too was a true believer in the church of RISC since I first used my friends Acorn Archimedes back in 1992 (I presume you know ARM used to mean Acorn RISC Machine...), but that was before I actually started using x86_64+avx512 extensively at an assembler level. Sadly, my large yellow-feathered friend, much of what you say points me to put you in the "biased by inexperience/outdated college tutors opinions" category as well, but I'm willing to entertain the ideas you've presented for a while, for the sake of consideration... Firstly, where did you get that "12 ALU instructions make up 89% of code" statistic, and which instructions are they? Does this mean 89% of ALU instructions (ports 0, 1, 5, 6), or are memory instructions (ports 2, 3, 4, 7, 8, 9) included? are branch instructions included? are we counting encoded instructions of µops? When was the study done, and what codebase? It should be noted that there are many excellent instructions in x86 that are simply inaccessible to the vast majority of programmers due to their operations not having a C/C++/"basically any language that does normal math" invocation. there's +-*/%^~ and that's about it, no room for tzcnt, lzcnt, pdep, pext, and many other more interesting bitwise operations except where the compiler/interpreter can discern that their use might be appropriate, or one must resort to compiler intrinsic functions, which aren't portable and discovering them is even more work than learning asm... Haswell is getting Very old by this point... I can't imagine there are many 4th gen CPU's still keeping up with even the basics of using the internet. My 3rd gen i7 laptop died a year ago, and before that it was reallllly struggling even with youtube... The re-ordering restrictions imposed by strictness of memory ordering is offset by speculative fetch execution, with backtracking if a speculative fetch subsequently is found to overlap with a forthcoming write. Whilst this process is not free, I do not feel I would want to have the risk of a subsequent iteration of a loop reading memory that has yet to be written by a previous iteration that hasn't completed yet, and processing based on incorrect data. The silicon for backtracking is required also for speculative execution of branches, so the cost is minimal. It occurs only occasionally so the performance hit is also minimal, and having everything always work as expected is invaluable, so I don't see your point. I'm not sure what you mean by "weird exceptions", unless you're referring to the 16-bit and 32-bit mode weirdness, but that is practically irrelevant nowadays. while the MUL and DIV instructions do have fixed register assignments, it's usually easy to work around without needing extra mov's, and they provide an option for 128-bit operands not available elsewhere. There's also IMUL which has 2-operand and 2-operand+immediate versions, and although it's intended for signed integer use, the result is identical for unsigned use except for the flags. And then there's MULX that is a 3-operand 64-bit multiply that doesn't set flags. Take your pick. the DIV instruction is quite rarely used, since dividing is one of the slowest operations in a CPU, but getting both the result and remainder in separate registers is very handy when you do (arm on the other hand has no modulo output at all, it has to be done by multiplying up the result of the divide and subtracting - though it also might be possible to get it more directly from a common multiply-based optimization of the divide operation). Of the 16 GPR's 15 can be used for basically anything, except the mul and div mentioned before, and the 2-operand variable shift instruction that can only use cl (low byte of rcx) as the shift amount. There's 3-operand mulx and sarx shrx shlx instructions that provide full register flexibility. The only GPR that's usage is special is the stack pointer, because it affects the stack engine that keeps track of call-return addresses. It's not the upper 8 registers that require the extra byte, it's using 64-bits, since the byte is also needed for the first 8 registers if you're doing 64-bit operations. Parity only checks the low byte of the register, but it's a legacy operation that only really applies to UART serial communication -- so what? I cannot speak to the cost to Intel or AMD of supporting the legacy instruction set, but it doesn't "flow through the whole design". Legacy instructions are decoded into modern µops for execution. There's a bit of extra ROM that has the µops for the legacy operation modes that no-one really uses any more. They look at what is being used, and make that fast, and support the rest by turning it into more of what is being used. But what I can speak to is that the instruction set isn't that hard to understand. The trick is to filter out the noise and focus on one section at a time. The Intel manual doesn't help with that since it is alphabetical rather than sectionized, but the process of sorting through that yourself is actually very helpful in getting an overview of the whole. I personally separate it into the following sections: 1 Ignorables: - legacy 16 and 32-bit instructions that are no longer relevant or even encodable in 64-bit code - x87 fpu instructions. SSE2 is minimum spec for x86_64 and everyone uses it instead - stuff to do with mmu and security levels that's only relevant to writers of OS's and HW drivers 2 Basics: - most basic GPR instructions, mostly used for address calculation and branch decisions 3 Advanced: - fancy bitwise and math related GPR instructions that make some interesting things possible 4 Basic Vector: - read vector from memory, do math, write vector to memory 5 Advanced Vector: - all the different ways of permuting/filtering/gather/scatter etc - fancy bitwise operations (ternlog, multishift, doubleshift, popcnt...), K-masks etc. 6 Optionals: - instructions that are only relevant to a specific but valuable ($B) use-cases, like the aes encode/decode instructions, fp16 instructions and tile instructions. Know they're there, look them up if you find yourself engaging in their use-case. I got fairly fluent in using 2,3,4 & 5 in about 4 months. It's not that hard. With the intel sdm & architectures optimization manual, and Agner Fog's instruction_tables.pdf, I got to the point where I could write code that makes full use of the hardware in about 6 months. I agree that it's a bind having to detect which instructions are available before starting work, but at least the progression has been linear. If you have avx512 you can basically guarantee that you'll have everything that came out before it, FMA, BMI2, BMI, avx2, avx, sse4,3,2,1... whereas risc-V's plug-in approach means that all you can rely on is the most basic base set of instructions, equivalent to group 2 above. The x86 ISA is not finished, it is a work in progress and always will be. Intel have been feeling their way forward into new ways of doing compute with the avx series, providing facilities and seeing what people would like to do with them and iterating on what they discover. With the most recent level of avx512 it seems almost complete (I can imagine a couple of instructions to make it even better but it's possible to do without), you can vectorise almost anything if you are willing to change how you think about it - and this is the biggest issue, that people struggle to change how they think, to let go of old data structures, algorithms, and ways of thinking that just don't translate into the new paradigm. And this is, in my opinion, the biggest issue with the avx512 instruction set: that old programming languages simply don't have the features to properly make use of the full capability of vector processing. Interestingly, it's functional language features like higher order functions that are closest to being able to make use of them, since they hide the details of iterating the dataset and can convert the given lamda to appropriate vector instructions. Expecting a C++ compiler to vectorize anything but the most basic loops is unreasonable. That universities are stopping teaching x86 is not a comment on x86, but on Universities. It's probably more to do with that it's easier to teach than that it's actually valuable to their students futures. RISC-V's simplicity is mostly a result of idealism, whereas x86's complexity is mostly a result of practical application.

@@treelibrarian7618 oscarlab.github.io/papers/instrpop-systor19.pdf That paper examines all the binaries of the entire Ubuntu 16.xx repo, so it's hardly a tiny study (though it doesn't examine dynamic instructions, looking into that yields similar results). I don't have the haswell study handy, but the fundamental situation isn't dramatically different today. Core size grows MUCH slower than Moore's Law (otherwise we'd still have just one core and it would use all those billions of transistors). You simply cannot make the case that strict ordering is better because of speculation. With weak memory ordering, you can do away with all that speculation circuitry entirely (and still have the option of including it if it boosts performance, but you'll still need less hardware). Put simply, there is nothing to lose and everything to gain from weaker default ordering. I'd also note that speculation is limited and will necessarily introduce false positives. This is especially interesting for JITed code where the JIT can potentially examine the runtime code and skip fences entirely for certain pathways. x86 manuals are several thousand pages with all kinds of weirdness through them if you take a look. It is considered extremely non-controversial to say that the ISA is weird. MUL and DIV are in tension with the A register. For example, let's say I have a loop that goes over an array and multiplies each number. I really want the incrementer to be stored in the Accumulator register and use fast, one-byte increment instructions, but if I do that, I must then add MOV each loop so it doesn't get overwritten by the MUL. I'm quite sure that there's another approach that does some other stuff, but that simply proves the point about weirdness. As to GPRs, A is special as accumulator. B is special as the base pointer for the segment register (more weirdness there). C is special as the counter register for shifts. D is special for MUL/DIV. SP and DP are special for stack instructions. SI/DI are special as index registers. I was being generous saying that 12 registers were actually general purpose. The response will be "but that's old stuff nobody uses", but that just proves the point about weirdness AND the point about inefficiency as all this stuff is guaranteed to the programmer by the ISA and winds up complicating hardware designs. Legacy isn't just about instructions. The PF flag (parity) that I mentioned is a very simple example. It adds another bit to EVERY SINGLE REGISTER. It also adds another pathway through the entire CPU design. This stuff isn't generic. ARM is making this exact argument right now in Qualcomm v ARM. They stated that the Nuvia (now Oryon) core is fundamentally so tailored to the ARM64 ISA that no part of it is non-ARM. Qualcomm made a big push to completely change RISC-V to basically become ARM64 because all that stuff DOES go through the entire pipeline and they'd be left redesigning most of the core otherwise. "Easy to learn" is relative. 4 months is a VERY long time when you consider that I could teach you all of RISC-V GCV in a week or so. I'm also 100% sure that after 4 months you didn't have a clue about all the weird tradeoffs that matter. There's reams of completely unintuitive places where there's multiple ways to do something. In the best case, you must learn which ones are footguns. In the worst case, you must learn when one is better and when another is better instead. Once again, RISC-V solves this issue because there's only ONE way to do common things and you can be completely sure it'll be well-optimized by the CPU. Along those lines, the extension argument about RISC-V doesn't make any sense for a few reasons. The first and most obvious one is profiles. github.com/riscv/riscv-profiles/blob/main/profiles.adoc If you implement RVA22S64, I know EXACTLY which extensions to target. This is the same as targeting i686 vs amd64 except the RISC-V stuff is better specified and actually gets decent updates. You mention "AVX-512 implies FMA", but does it imply FMA3 or FMA4? Which AVX-512 extensions? NOTHING supports all of them. Even if we disregard profiles, checking for extension support is easy. It's baked into your compiler and is already done in EVERY major ISA you can name. x86 is mostly finished if for no other reason than its running out of encoding space that uses less than 6-7 bytes making new instructions massively inefficient. RISC-V was beating x86 in code density 9 years ago with C instructions making the average instruction just 3 bytes long. Since then, new instructions like bit manipulation have further increased the code density lead. I-Caches aren't really growing in size and x86 instructions can't really improve. This is another major advantage that proves the "every ISA is the same" argument to be false. en.wikipedia.org/wiki/Turing_tarpit All Turing Machines are equivalent in capabilities, but are self-evidently not the same in reality. Ascalon is an 8-wide architecture that Jim Keller expects to compete with Zen5. The entire Tenstorrent company is 280-something employees. Many of those employees aren't engineers and many of the engineers are working on smaller RISC-V cores or their AI accelerators. In reality, it's more like 100 engineers and QA at Tenstorrent are making a chip that requires thousands of engineers at AMD or Intel. This isn't just being a startup. It's because RISC-V is designed for this purpose. We know all about headspace in the programming world. You can only hold a handful of things in your mind at one time. The more complexity, the more bugs and the slower the development progresses. This is why the first 80% happens so much more quickly than the last 20%. We reached the limits of assembly very quickly and moved on to FORTRAN then C. We hit the limits of those and moved to the OOP craze with languages like Java. Even that wasn't high enough, so we saw Python, Ruby, JS, and others bloom. Those are reaching their limits and we're now seeing a push into functional paradigms that trade a bit more efficiency for the ability to write even larger projects in a sane amount of time. Simplicity in the RISC-V ISA wasn't just about teaching. There's a lot of research going on about how to increase IPC of chips because we've maxed out realistic clockspeeds in silicon (even theoretical limits of silicon are around 10GHz IIRC). You MUST go a lot wider, but going wider gets you into crosscutting concerns which immediately trash your chip development pace. All the decisions to reduce the interface with the programmer also helps reduce the need for these speedbumps. Even more importantly, the ISA was explicitly designed to reduce side effects instructions and by proxy, keep the ISA separate from the uarch as much as possible so decisions you make in the uarch don't bleed over to the consumer. RISC-V is interesting in that it is both easier than x86 and also practical. Qualcomm shipped 1B RISC-V cores in 2023 and they aren't even the biggest RISC-V company and most of their chips are still ARM. Nvidia and Western Digital have shipped billions more. RISC-V has basically done a complete takeover of FPGAs because you not only get free high-quality cores, but an entire high-quality software ecosystem to match. This is all without mentioning China or India which are making absolutely massive investments into the ISA as are companies like Google. Even Intel and AMD paid for seats at the consortium table with Intel manufacturing a SiFive core combined with all Intel's proprietary IP in an attempt to get more non-Intel chips made at their fabs. I fully expect to see either Intel or AMD update their core to allow RISC-V execution (this is easier than going the other way courtesy of RISC-V trying to isolate the ISA from the uarch). I'd encourage you to take some time to learn RISC-V then compare. I think you'll be shocked at how much easier it is and that 4 months would render you an expert rather than simply knowing the basics.

I had completely forgotten that fact, but that's right!

Ah, the K6... the first cpu I bought myself was the K6-2 600...

afik, amd still has those instructionsets from k6 era

@@betag24cn No, 3dnow! is obsolete and got removed from newer AMD CPUs. There was an agreement about the SSE family of instruction sets, thus 3dnow! was no more needed and it was incompatible with SSE.

@@OpenGL4ever now that youmention it, i have not checjed that in many years, probably you are right

64 is RAX

Assembly level debugging and optimization are black magic

Most calling convention uses RAX for return value, the naming conventions are just legacy, it's not actually used as an accumulator. RBX is not the base pointer, that's RBP, there is no RSB register. What instructions only work with certain registers? This just isn't true I believe. Atleast for the general purpose 16, maybe SSE, AVX, or XMM registers are instruction specific idk we haven't got that far in my class yet.

@@virno69420 base in rbx doesnt mean stack base, it means memory base which is what it originally was intended for. and some instructions do use the registers with their original intention, like div, rep, movs etc...

@@thewhitefalcon8539 I edited to clear some things up, and fixed that typo.

Yes and they used to make them using lithography before they went with photo-lithography so then there was another literal die.

are you talking about itanium or something else?

@@radfordmcawesome7947 yes. Intel has also recently proposed a new X86S architecture.

it was mostly microsofts fault really, microsoft windows is a legacy of code, nothing modern in it, not since windows 2000 basically with the arm windows project that should deliver some devices this year, perhaps that finaly happens, without intel it seems

I don't think so. The Apple Macintosh stated on the M68000, then switched to PowerPC with support (an OS built-in emulator) for M68000 apps, which then switched to x86, which still had both PowerPC and M68000 support, then they switched to x86_64, which you may think was an easy jump, but probably required quite a bit of code page management in the OS, then they switched to ARM. Although they've dropped some of that emulation along the way, you can still get it, and things still can work as they always have. I think Windows and Linux could do the same. with QEMU in Docker, containers already do some emulation with buildx, so it's not too far of a jump.

@@jaysistar2711 I assure you that gamers unwilling to take the performance hit associated with the emulation will stop the switch dead in its track. With Mac the thing is that a) it's a single machine by a single company so people literally have no choice but to switch if they want to use newest and best (debatable...) products, not thousands machines by thousands companies, some even being DIY affair, and b) Mac never really did games very well. Try running Cyberpunk 2077 on a mac. You can't. Or at least, you can't run it well.

@@jaysistar2711 The only reason why apple can do arm is because it's a horrible monopoly and people complained about the very real issues the switch caused. You're basically saying "The company store can switch and deprecate currency every year, why can't the government?" The answer is that it only exists due to artificial reasons ( You being horribly in debt to the coal company or either being too dumb to leave apple or unable to due to them grabbing your work software in their malformed tentacles).

@@UltimatePerfection I agree that Apple products are overpriced versions of inferior hardware, but I disagree about a performance hit being required to exist if the PC switches to another CPU because I don't know of any native version of the x86_64 at this point; the whole x86_64 platform is emulated on both AMD and Intel chips. Also, REDengine (Cyberpunk 2077) is a cross platform engine. It can run on the Switch (ARM), but doesn't because GPU performance and capability (ray tracing, API support, etc.) is more important for games than what CPU ISA they use. I've ported hundreds of games commercially, and I can tell you that Apple's mistake was in making Metal the only option moving forward. That's just more work, and, as a game engine dev, we're an overworked bunch as it is.

@@jaysistar2711 Yeah... x86_64 being emulated on an x86_64 processor... Nice try, but no dice.

soon

X86_64ex*

Unlikely, intel has tried twice to change the x86 platform. Itanium, and pentium 4. Both failed, so anything they do will have to be backwards compatible.

In 2020. However, x86_64-v2 is a codename for CPUs with at least SSE4_2 and SSSE3. (which was supported already by 2008 CPUs). For comparison, x86_64-v3 means roughly support for AVX1 and AVX2 (CPUs from 2014 and later) x86_64-v4 is with support for AVX512, but this one is a can of worms

@Kaznovx OK you meant that. But that is an unrelated topic, as it is about common baselines.

He could have forgot it happens

Not in every institute. Nowadays, lower level stuff are studied more by electrical engineers than computer scientists. Also, people forget.

IIRC virtual memory explanation isn't a part of courses required for BSc in CS🙃

​@@bbourbakiyou don't need to be a low level guy unless embedded and even then there is still abstraction

@@bbourbaki Do you know what fixed parameter tractability is?

Yes but it's better than no option at all.🙃

when we had via, it wasnt a option reallyrigth now you have two, but i wouldnt touch anything from intel

​@@joseoncrackwell, in apple, there is no option and people is happy on android smartphones you dont choose, you choose the whole device it is nice to have options but sometimes things do work like that

Only 2 options for x86 CPUs is down to US government being feckless and derelict in its duty to break down monopolies (well, duopolies here but you get the gist). They let Intel/AMD use the x86 patent pool to completely own x86, to the detriment of everyone else. Citizens United lets big companies bribe politicians and this is how we got here.

@@betag24cn It's good to have options. But yes, obsessing over it doesn't change a thing either: like, here, many people seem to absolutely despise the x86 architecture (often without even really knowing what it is now), but it just works well enough (at least on the desktop and server markets) and you'll be hard-pressed to find anything with the same performance at this price range. In terms of performance, one exception (really an exception for now) are the Ampera CPUs (128-core ARM-based), and these are still niche products, very expensive. The day there are alternatives to x86 for the same kind of applications, with as much performance and for the same price, but with more "modern" architectures, people will eventually switch en masse. But that's just not the case yet. It is for mobile devices, and has been for years, though, which is a market Intel has always struggled with.