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Booting code from a ROM implemented using a Verilog case statement, disabling DRAM refresh, and eliminating wait-states to speed up instruction execution speed.
Check out the discord: / discord
Github repo for this CPU board: github.com/johnwinans/2067-Z8...
Github repo with the FPGA board that this plugs into: github.com/johnwinans/2057-IC...
Github repo for the Verilog Examples: github.com/johnwinans/Verilog...
Z80 Nouveau Playlist: • Z80 Nouveau
FPGA board video playlist: • FPGA
You can support this channel on Patreon! / johnsbasement
Music used in this video (Vibe Tracks, Alternate) was downloaded from the KZfaq Audio Library.
#verilog
#z80