Analog Layout & Design

Пікірлер

@kollasivaramakrishna6732 2 күн бұрын

good explanantion

@analoglayoutdesign2342 Күн бұрын

Thanks

@AllenSA_Lymangirl 7 күн бұрын

Thank you for explaining this conpect in a lucid way...

@analoglayoutdesign2342 6 күн бұрын

Thanks for the feedback

@anilkumarpattapu4309 10 күн бұрын

Only it provides constant ouput v or i respective of temperature variations? It is not if voltage supplay varies will not vontrol,

@analoglayoutdesign2342 9 күн бұрын

This architecture provides constant voltage and ptat current. Sub 1v architecture provides constant voltage and ztat current

@dasarinikhil14 21 күн бұрын

Hi Sir i have a dout like why the channel will send week signal to rx , as it's giving strong signal , is it due to capacitence or any other , please clarify this one by anyone

@analoglayoutdesign2342 20 күн бұрын

Yes it’s due to RC of the channel

@dasarinikhil14 20 күн бұрын

@@analoglayoutdesign2342 thanks sir

@dasarinikhil14 15 күн бұрын

@@analoglayoutdesign2342 help me with how we do placement and floorplan on What bases we will do it

@sreedevigiri723 25 күн бұрын

Exceellent explanation sir. Thank you

@analoglayoutdesign2342 24 күн бұрын

You are welcome

@eCiderr 29 күн бұрын

This is very well done! Thanks!

@analoglayoutdesign2342 29 күн бұрын

Thanks for the feedback

@sasa_agha_87 Ай бұрын

Many thanks!

@analoglayoutdesign2342 Ай бұрын

You're welcome!

@gopisureshchowdary Ай бұрын

Hi sir.Your videos are very helpful layout engineers. Can you please make videos on Antenna Effect Practicality?

@analoglayoutdesign2342 Ай бұрын

Ok will try

@shivamgautam130 Ай бұрын

Very informative Sir, Thank you

@analoglayoutdesign2342 Ай бұрын

You are welcome

@offscreensingers7644 2 ай бұрын

Thanks for your clear explanation bro.❤❤

@analoglayoutdesign2342 2 ай бұрын

Thanks

@mahadesharya6975 2 ай бұрын

Excellent professor. Thanks a lot. I had watched ESD series on this channel long back

@analoglayoutdesign2342 2 ай бұрын

Thanks

@vijanvijan1936 2 ай бұрын

Mosfet capacitance video sir

@analoglayoutdesign2342 2 ай бұрын

Is it not covered?

@rohitshelkar7525 2 ай бұрын

your content is very good, could u please make some more videos on Serdes. Also, it would be helpful if you share the resources for study.

@analoglayoutdesign2342 2 ай бұрын

Ok will do.. need time

@bhavanavalaboju6098 2 ай бұрын

Hi sir, thank you for the useful content. Consider APmom capacitor using 22nm fdsoi. a) I increased the oxide width from 1u to 1.033u, the cap remained same with 11 fingers (the device is automatically taking the number if fingers as 11). b) But when i increased the width to 1.034u, the cap increased and the number of fingers automatically increased to 12. Doubt: what changed during a) such that the cap value remained the same. Thanks a lot.

@analoglayoutdesign2342 2 ай бұрын

In case a, you only increased the width of insulator. Not the thickness. If you had increased the thickness of insulator, then cap would have decreased. But it’s a process thing and you can’t increase insulator thickness. Width of the insulator will not have effect on cap value. In case b, you changed the metal width, now cap has to change and it did. Hope this clarifies

@bhavanavalaboju6098 2 ай бұрын

@@analoglayoutdesign2342 Thank you for the response sir. But in a) as the width of the oxide increases, the area of the metal that holds the oxide in between also increases.(The number of fingers are 11 by default). This should increase the cap. In b) I did not increase the metal width, I just increased the width of oxide from 1.033u to 1.034u (which increased the number of fingers to 12 automatically). I do not understand what exactly happened with the cap when the width of the oxide is increased from 1.033u to 1.034u

@analoglayoutdesign2342 2 ай бұрын

So, the cap is fixed till number of fingers are same. That’s may be manufacturing accuracy. You may check the extracted netlist cap. May be that will change when you increase width of oxide without increasing the fingers

@bhavanavalaboju6098 2 ай бұрын

@@analoglayoutdesign2342 okay, thank you.

@pallavisingh9973 2 ай бұрын

please also make video on how to simulate in cadence

@analoglayoutdesign2342 2 ай бұрын

I also want to do that actually

@pallavisingh9973 2 ай бұрын

Please make🙏

@pallavisingh9973 2 ай бұрын

which diode is choose in the cadence? please make some video on cadence please......its my request

@sigityuwono9902 2 ай бұрын

paused 16:00

@Ashish-gb4vg 3 ай бұрын

28:16

@arasha9047 3 ай бұрын

If you put pwell under box and n+, it cant be biased positive.

@ShivaKanugula 3 ай бұрын

Please do make a video on Antenna effect & STI/LOD

@analoglayoutdesign2342 3 ай бұрын

Will plan.. thanks for your suggestion

@piezero_567 3 ай бұрын

For ptat ckt. Generation are we taking beta of the bjt as infinite because only then base current is negligible....?

@analoglayoutdesign2342 3 ай бұрын

Here bjt used as diode.. it’s now variation of vbe as pn junction

@vimakuma 3 ай бұрын

Hi sir. @20:51 can not we just short 1v nodes of both cascode mirrors? Ultimately they will become same when we just connect them.

@analoglayoutdesign2342 3 ай бұрын

Please go thru.. we can’t do it that way

@vimakuma 3 ай бұрын

Could you please explain PLL sometime??

@analoglayoutdesign2342 3 ай бұрын

Ok will try with introduction video

@vishakhabhale4584 3 ай бұрын

very good lectures.....but sir one suggestion for you....please use good quality mic....your voice has air disturbance. may be you are talking very near to mic.

@analoglayoutdesign2342 3 ай бұрын

Noted

@srinidhi273 3 ай бұрын

It's wrong you have given positive feedback to error amplofier, it should be negative feedback.

@analoglayoutdesign2342 3 ай бұрын

Please go thru the video.. everything is explained.. no body will explain to you by coming down to such low level of basics

@vimakuma 3 ай бұрын

Whenever I get rejected in any interview and can't explain how the latch up works. I just come here and revise my basic 😭😭😭

@analoglayoutdesign2342 3 ай бұрын

Always be prepared.. if you understand the concept, no need to prepare again and again

@sailakshmi6278 3 ай бұрын

I think 3rd case was wrong only m1. Is on m2 is off bcz vgs less than vt in pmos vgs is 0.9 but vt is 0.6 m2 is off condition

@randomsstudioo 3 ай бұрын

great explanation

@analoglayoutdesign2342 3 ай бұрын

Thanks for the feedback

@vijanvijan1936 4 ай бұрын

Ur really great sir....i get clear understanding

@vijanvijan1936 4 ай бұрын

Thanks

@riptideriptide6945 4 ай бұрын

waaaa，great welcomeback

@learner0000 4 ай бұрын

There is a load here ummm circuitry here 😂😂, I like the way you trying make it more simpler and simpler, this is what we need from lecturers before using a technical term, lecturers need to make the students understand what it's meant for

@chandanasudunagunta8230 4 ай бұрын

Sir very understandable explanation, y only latch up occurs in final stage of drivers only, please clarify. Thank you

@analoglayoutdesign2342 4 ай бұрын

Hi.. it’s explained in the video only.. where you have big transistors NMOS and pmos, the parasitic npn and pnp transistors form.. otherwise, for every small inverter, there would be latch up and cmos process could not be used at all..

@sharathseshadri3634 4 ай бұрын

why can't we use p+ in DNW

@analoglayoutdesign2342 4 ай бұрын

Why du you want to use?

@sharathseshadri3634 3 ай бұрын

I want to know what happens

@gamedevunity3dliviopanizzi170 4 ай бұрын

hi , but the resistor on chip how they are do it ? grazie

@analoglayoutdesign2342 4 ай бұрын

In some foundries, they have high sheet resistant metal layer… they form resistors in that metal layer

@gamedevunity3dliviopanizzi170 4 ай бұрын

thanks@@analoglayoutdesign2342

@tanluu1944 4 ай бұрын

All your videos are great, please make a video on LNA. Thank you.

@analoglayoutdesign2342 4 ай бұрын

Thanks for the feedback.. will do

@gauthamkrishna6626 4 ай бұрын

@@analoglayoutdesign2342... Plss make it..Thanks Sir

@abhijeetbisht9942 4 ай бұрын

Wonderful video🙏🙏

@analoglayoutdesign2342 4 ай бұрын

Thanks for the feedback

@tanluu1944 4 ай бұрын

Thank you.

@analoglayoutdesign2342 4 ай бұрын

Thanks for the feedback

@taraldc 4 ай бұрын

Very very nice explanation .. very good job Sir.. Everything is crystal clear.. Please carry on such a good work

@analoglayoutdesign2342 4 ай бұрын

Thanks for the feedback

@ammaryasser8078 4 ай бұрын

Ooh welcome back sir :D

@gopisureshchowdary 4 ай бұрын

Hi Sir.Awesome series for who wants to start their career in Analog Designer.We are expecting some videos on Matching Techniques (Common Centriod,Interdigitzed).Practical way of approach .Could you please upload those ?

@analoglayoutdesign2342 4 ай бұрын

Yes will upload one video on matching techniques of transistors