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@MsRajesh456 2 күн бұрын
2^16 😂 is not 256 right. 2 ^8 is only 256🎉❤
@KIRUTHIGAK. 7 күн бұрын
mam now in 2024 it is important to learn vhdl or verilog
@vlsiforyou 6 күн бұрын
70% verilog 30% vhdl
@KiruthigaKumaran-zh9kq 6 күн бұрын
@@vlsiforyou Thanks a lot mam
@mercyabida6515 8 күн бұрын
❤🎉
@mercyabida6515 10 күн бұрын
❤🎉
@mercyabida6515 11 күн бұрын
❤🎉
@mercyabida6515 11 күн бұрын
❤🎉
@mercyabida6515 11 күн бұрын
😂😂😂😂 .*🎉❤
@mercyabida6515 11 күн бұрын
😂❤🎉
@vennilas9893 12 күн бұрын
Great explanation. Please post UVM videos, it would be very helpful mam
@vlsiforyou 11 күн бұрын
Sure! Thanks for you support
@haryneevs3995 20 күн бұрын
module carry_look_ahead_4bit_tb; reg [3:0] a,b; reg cin; wire [3:0] sum; wire cout; carry_look_ahead_4bit dut(.a(a), .b(b),.cin(cin),.sum(sum),.cout(cout)); initial begin $dumpfile("dump.vcd"); $dumpvars(1); a=0; b=0; cin=0; #10 a=4; b=2; cin=0; #10 a=7; b=5; cin=0; #10 a=3; b=5; cin=1; #20 $finish; end initial $monitor( "A=%d, B=%d, cin= %d, sum=%d, cout=%d,A=%b, B=%b, cin= %b, sum=%b, cout=%b", a,b,cin,sum,cout,a,b,cin,sum,cout); endmodule this is the testbench I have a doubt that can I assume any values for a,b,cin
@haryneevs3995 20 күн бұрын
can i write like this is this correct
@vlsiforyou 20 күн бұрын
Any value you can give to a, b, c inputs
@haryneevs3995 19 күн бұрын
Ok mam
@meathamaganathan7250 22 күн бұрын
Mam na epa than b.e electrical engineering la vlsi eduthurkan enaku syllabus enna nu theriyala aprm enna la engineering exam lam attend panna mudiyuma pls rly mam
@vlsiforyou 21 күн бұрын
Syllabus pathi enakku therila, unga regulation ku search panna kidaikkum mostly. Illana unga professor kitta kelunga
@Saiprashanth-sf7bf 29 күн бұрын
Please upload how to write a Test bench in system verilog
@vlsiforyou 29 күн бұрын
Ok, will do it
@vijinjoe Ай бұрын
🙏
@vijaymosco2832 Ай бұрын
Very useful Mam....🤝🏻
@vlsiforyou Ай бұрын
Thanks for your support
@sangeetha-nu6vp Ай бұрын
Akka pls continuous ah video upload pannuga. Romba helpfull ah iruku. UVM concept quick ah podunga❤😊
@vlsiforyou Ай бұрын
Kandippa, concept ready panni, prepare panni video poda time edukuthu. Sure ah uvm cover pannituven
@Saiprashanth-sf7bf Ай бұрын
please upload more constraint interview questions like this mam ,your work is so much great. now i able to understand the constraint mam thank you so much
@vlsiforyou Ай бұрын
Thanks for your support! Most of the constrain interview questions are covered. We have uploaded constrains videos ( from SV21). In those videos, we covered constraint interview questions also. Please take a look 👍
@arunkumarmarimuthu1405 Ай бұрын
Please upload functional coverage
@vlsiforyou Ай бұрын
Sure, will be covered after interface
@hariharankrish6323 Ай бұрын
Dollar display and dollar monitor ku difference sollunga sister Tamil la....simulation result la ena changes nadakum nu sollunga
@vlsiforyou Ай бұрын
Refer #14 display tasks in verilog, I have explained detailedly
@_VISHNUPRIYAK-hc5si Ай бұрын
Mam..pls.give some guidance about available open source software for vlsi project.
@vlsiforyou Ай бұрын
For experience, you can use EDA Playground.
@sumkrisheditz 2 ай бұрын
8:58 Two methods I have mam, please review it 1. val[i] = fact ((( i + 1 ) * 2 ) - 1 ) 2. val[i] = fact ( i + ( i + 1 ) )
@vlsiforyou 2 ай бұрын
Yes, both are correct.
@sumkrisheditz 2 ай бұрын
Hi Mam. If we do right shift will it generate only the One's? constraint c1 { data == 1 >> shift ; }
@vlsiforyou 2 ай бұрын
No, we will get 0 for right shift
@sumkrisheditz 2 ай бұрын
Ohh Okay.
@selvaraj.ca143 2 ай бұрын
Please we need a regular videos ,atleast 4 videos in a week mam and pls post videos in Interprocess Communication SystemVerilog Program Block SystemVerilog Clocking
@vlsiforyou 2 ай бұрын
Thanks for your support. I'll try to do it. It's taking more time to prepare, workout, record, edit and upload the video. I am trying to give my best of knowledge. I hope you all understand us.
@selvaraj.ca143 2 ай бұрын
I'm grateful for your work mam,ur the one and only source to learn SV and Verilog In tamil with Great understanding mam.Thank you so much mam .Keep doing it mam .
@harshinij6327 2 ай бұрын
wonderfull teaching mam ♥ Thank you for the SV playlist.
@vlsiforyou 2 ай бұрын
Thanks for your support
@PRAVEENM-xy3is 3 ай бұрын
%2d %2s defines?
@vlsiforyou 2 ай бұрын
d and s are print formats d means decimal and s means string 2 is for space after equal to Example - $display("a =%2d",a); Assume a = 1, Result : a = (space)(space)1
@mekalamekala8214 3 ай бұрын
Mam oru standard course pannanu with job offer,ethachu trusted website sollunga
@vlsiforyou 3 ай бұрын
Really I don't know about the online courses. But you can find reputated institute for learning and job offer.
@yuvarajkamalakannan8140 3 ай бұрын
mam pls ensure audio quality. use any audio filter application like dolby on or any similar app. better you must use mic with noise cancellation feature. Apart from all hats off to your effort to make a tech video in tamil. All the very best for your long tech journey.
@vlsiforyou 3 ай бұрын
Thanks for your support. Yes, we implemented our audio quality for further videos. We are using microphone
@user-zp1ts3mv4s 3 ай бұрын
Please cover all the topics on system verilog and uvm...
@vlsiforyou 3 ай бұрын
Yeah, will cover soon Please subscribe us and share with your friends And follow us on Instagram for any queries
@user-zp1ts3mv4s 3 ай бұрын
Super sis👏👏Thanks for making videos on system verilog.Do more videos sis!!!!!
@vlsiforyou 3 ай бұрын
Thank you, I will
@divyaramamoorthy3450 3 ай бұрын
Upload next video mam🙌
@vlsiforyou 3 ай бұрын
Will upload soon
@boopathim3426 4 ай бұрын
Pls try to upload 2-3 videos weekly akka it will be helpful for us!
@imvkumar518 4 ай бұрын
Super akka 👍 please continue...
@vlsiforyou 4 ай бұрын
Sure
@gokulp6878 4 ай бұрын
really good.can you please exaplain axi or ahb protocol?
@vlsiforyou 4 ай бұрын
Sure, will be done in upcoming videos
@gokulp6878 4 ай бұрын
@@vlsiforyou thanks
@sumkrisheditz 4 ай бұрын
UVM videos post pannunga mam plsss ..
@sumkrisheditz 4 ай бұрын
UVM videos post pannunga mam plsss ..
@vlsiforyou 4 ай бұрын
Will upload soon
@divyaramamoorthy3450 4 ай бұрын
Please upload next video mam
@vlsiforyou 4 ай бұрын
Sure I will
@ECEManjudeviM 4 ай бұрын
Thank you mam its very helpful for me ❤
@vlsiforyou 4 ай бұрын
Most welcome 😊
@sunpictures5889 4 ай бұрын
system verilog videos avlothaana mam!
@vlsiforyou 4 ай бұрын
Inam iruku, Will upload Soon
@sunpictures5889 4 ай бұрын
vlsi ku tamil la video ninga matumthan podringa so neraya podunga mam,please company vera vara poguthu🙏🙏🙏🙏
@sunpictures5889 4 ай бұрын
mam video podunga mam,aduthu ena padikrathunu terila mama please
@imvkumar518 4 ай бұрын
val[i]=fact(((i+1)*2)-1);
@vlsiforyou 2 ай бұрын
Correct
@vennilas9893 4 ай бұрын
Good and clear explanation on concepts. Keep posting
@imvkumar518 4 ай бұрын
Your videos easy to understand , continue....
@imvkumar518 4 ай бұрын
randc use panna same number varathula because we want only 15 values but we have 32 values also logic is good 👍
@imvkumar518 4 ай бұрын
randc use panna same number varathula because we want only 15 values but we have 32 values also your logic is good 👍
@imvkumar518 4 ай бұрын
Arr[i] %2 !=0;
@vlsiforyou 2 ай бұрын
Correct
@imvkumar518 4 ай бұрын
Useful video 👍👏
@imvkumar518 4 ай бұрын
Thank you
@imvkumar518 4 ай бұрын
Super akka
@imvkumar518 4 ай бұрын
Thank you mam very useful video
@imvkumar518 4 ай бұрын
Thank you mam