Constraints - Foreach and Inside Concepts | SV#23 | VLSI in Tamil
Рет қаралды 243
6 ай бұрынThis video contains #foreach and #inside #constraints in #systemverilog
5:53 - Interview Question 1 (Foreach)
9:15 - Interview Question 2 (Foreach)
9:30 - Interview Question 3 (Foreach)
12:35 - Interview Question 4 (Foreach)
17:30 - Interview Question 5 (Inside)
19:30 - Interview Question 6 (Inside)
Constraints - The Basics
• Constraints - The Basi...
Randomization
• Randomization in Syste...
Encapsulation
• Class Part 7 - Encapsu...
Polymorphism
• Class Part 6 - Polymor...
Inheritance
• Class Part 3 - Inherit...
#vlsi #vlsidesign #halfadder #fulladder #testbench #verilogcode #mux #constraints #encoder #staticproperties #randomization #staticclass #coverages #inheritance #static #parityencoder #module #carrylookaheadadder #verilog #systemverilog #uvm #vlsiprojects #vlsiforyou #v4u
@gtcontent3069 6 ай бұрын
Hi madam, a[i]%2 != 0 means odd numbers lam generate agum. constraint ccc {foreach (a[i]) { a[i]%2 !=0; if(i>0) a[i] > a[i-1]; } }
@vlsiforyou 6 ай бұрын
Your answer is correct! 👍 Keep it up
@imvkumar518 4 ай бұрын
randc use panna same number varathula because we want only 15 values but we have 32 values also your logic is good 👍
@imvkumar518 4 ай бұрын
randc use panna same number varathula because we want only 15 values but we have 32 values also logic is good 👍
@imvkumar518 4 ай бұрын
Arr[i] %2 !=0;
@vlsiforyou 2 ай бұрын
Correct
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