Watching this during the Corona Lockdown, when there are no Uni lectures and i was feeling totally lost! man thank you so much.

for the second configuration a separate state table has to be made as the outputs are now changed. In 1st configuration they were in complement form i.e. Qa' Qb' Qc' but now in 2nd configuration they are as Qa Qb Qc . And while you analyzing the values of Qa, Qb, Qc i.e. output of 2nd configuration ( 8:29 - 8:37 ) you have compared it with the 1st configuration state table which making all the confusion in the audience.

Thank you sir for making video with great explanations.

In the second configuration, why did you start taking ouptput from the secomd clock pulse , and not from the initial state like you did in the first configuration?

The best explanation i have got on counters so far

In the second circuit , set values of qa' qb' qc' as 1 initially and analyse qa qb qc accordingly .

for down counter consider from pulse 1 as it gives decimal 7... continue till 8th pulse to get 0. pulse 0 is not considered as we assume all flip flops to be in power down state (no memory stored so Qa, Qb & Qc are 0 initially) 0th pulse is same as 8th pulse

thanks for your great effort

Sir, You are my life saviour! The word thanks is not enough to show my gratitude..

I dont understand in the second circuit you are complementing Qa prime before feeding it in the clk of Qb. So is that not the same of feeding Qa in the clock of Qb? does that not make it positive edge triggered?

Sir in the waveform diagram of down counter it looks like it is positive edge triggered rather than negative triggered. But you had said that down counter is negative triggered as well.

in the second circuit the graph or truth table follow the downward counter for complement outputs but how can you get the downward counter from not not complement outputs?

awesome lecture, thank you!

i dont know how best i can thank you for this great lectures. please you have been using negative edge flip flop, if its positive edge, what will be the timing diagram?

Awesome lecture series ❤

Thank you very much!

Thank you for the video. Great job you have done. But as far as I can see these two methods don't have the same result. In the first method initially it is 111 (as the compliment of 000) and that is fine, but in the second method we have 111 at the first impulse, and initially it is 000. Please comment.

Thank you for you videos...

THANK YOU so much sir

sir did u had inverted the o/p? in both of the configuration

In the second configuration of the 3-bit up counter where you feed the negated flip flop output, why do you start the counting from the 1st clock pulse?? why do you not assign the value for the initial clock pulse??

What happens if both the output and the clock to the next flipflop is taken out of negated output of flipflop? It still gives down counting right? Thanks

sir, it is necessary to show second circuit condition on waveform ???

just awesome sir

what happens when the 8th clock pulse edge is applied i mean does the counter go back to 111 ?

sir in second circuit what u considered initially is zero Qa=0,QB=0,QC=0 fr initial state

Difference between up and down counter?? Does it depend on if we are giving logic state high or low??

It is also possible to use positive edges instead of negative edges in a up counter to turn it into down counter.

sir u are great....i like the way u explained...thanks a lot..

Man you are awesome

In the second circuit ,initially we are taking 000 but initially there 010 because clock of second flip flop is already 1 as it is connected to qa complement which initially is 1 as qa is zero initiaally .pls explain

I have a question that why don't you use positive edge triggered FF's, can you pls explain!!

Everything that is concievable is clearly stated. Geat job.

How did we get graph(rise/fall) for the last Qc?

Thank You Sir

we can also use positive edge triggering

loved it...Nice content..

in 2 nd method of down counter, for making waveform of Qc, can it is not follow the compliment of Qb of the previous method??

thx for the help

Just one suggestion.. Plz try to always tell about the next presentation topic so that it is easy to follow the lectures.. Coz youtube sometimes doesn't show the next video.. Or you can either number your videos.. That would be even better.. Nice work btw.

Can i design a mod-5 asynchronous counter without using CLEAR Pin? I may use some sort of combinational circuit. Please Reply

don't we need to take preset for all flip flops in the second diagram? then only all the outputs would be high for first clock pulse right?

Thank you sir

Thank you !

At 8:20 you're reading 1,1,1 from the 1st clock pulse (triggering) but writing it down after initially in the table. Why is that so?

In my text book, the down counter operates with Q1=Q2=Q3=1 at the initial state, not the complement of them equal to 1 (in which Q1=Q2=Q3=0, this is the initial state of UP counter). Hope you check it again. And anyway, you’re doing God’s work, keep it up. Thank you.

i have a doubt.in practical experiments,how do we connect preset and clear to ic chips in a bread board

Thank you so much sir 😊

for -ve edge trigger please explain the waveform for down counter without taking up counter compliment,

here we are considering before first clock pulse Qa as 0 (zero ) what if it is 1 from initial ?

thank you very much

please help as to how in the second circuit u start taking output number 1 after 1st clock pulse and u don't take the initial state 000 into account..as you have done for other counters

sir why you made 3 flip flops in 3bit and 4bit synchronous down counter??

Hey buddy. You are awesome man. Just splendid.I have completed a chapter from your Channel. I will be grateful to you vai.I am a Student of class Eleven. From Bangladesh 🇧🇩🇧🇩🇧🇩. Love you😘😘

What will be the output if i take clock and output both as complemet (Qa,Qb,Qc)

thank you

If I want Q as output and Q only as a clock to nxt Flipflop then down counter be achieved using positive edge triggered clock.

which circuit gives efficient design sir ?

Do I need to show both original outputs(i.e QA, QB, QC) and the complement of the outputs in the time diagram?

can we use T flipflop instead of jk to logic -1?

Bro ur god during exams

Was there a 4bit down counter diagram?? I didn't notice any, please provide timestamp.

i will contribute to you once i will start earning thankyou soomuch

you can use the up counter with positive edge triggering for down counting.but the initial state will be 0 and then it starts down counting from 2^n - 1.n = no of FFs

ur videos are very helpful. In the second configuration of the 3-bit up counter where you feed the negated flip flop output, why do you start the counting from the 1st clock pulse?? why do you not assign the value for the initial clock pulse??

Thank You, Great Videos, Nice English.

Dear Neso Academy, can you have a lecture video about asynchronous system: how to make the flow table, how to reduct the state through partitioning and using merge diagram. Or an example problem like vending machine? I hope you can help me. Thank you.

for the second config isnt it initially 000 ?

Fantastic

Sir why u r not taking the initial values while calculating Qa,Qb, Qc for the 2nd ckt....pls solve this

thank you sir :)

Down counter’s wave form wrong , u have to take Qb on the bases of Qa’ and then u have to take Qb’ but u take Qb on bases of Qa . Am I right or wrong

I don't understand it can you explain it for the down counter for 4 bits?

thankyou dude

For 4 bit down counter ...t flipflop use or j k flip flop??

but sir u use initial stage for 7 in first circuit and in second circuit u use first falling edge to show decimal 7 ?????

in the second config the counting starts from 000 then 111 then 110 and so on ....

Can you plz explain for up and down by using d flip flop?

Using second method we have 000 initially and 111 for 1st falling edge, and we should consider initial pulse which makes the answer wrong. Someone please help me clarify the concept.

Mention msb and lsb for second configuration please..

Sir the title was down counter but you drew the table for up counter I didn't get it

Life saver before the exam ...

can u start with 2nd configuration 1st , 1st one is easy to understand but 2nd one gets messed up with 1st one ?

Clock is negatively triggered or positively trigvt

please upload Analog electronics video too.

In the second configuration of the down counter where we feed the negated flip flop output to the other, how do we start at '111' when Q_A is 0 initially?

Best sir👌👌👌💐💐

No one can beat neso academy in terms of detailed explanation

Pls upload any asynchronous sequential ckt problem

what is logic 1.how do we connect it while wiring ic chips

Hello, how do I make it count down from 5 to 0?

Can't we take the output of the complement when complement is given as the clock?

I was experimenting. Used same up counter, but with positive edge triggering, and my result was down counter. Is that true, or I made a mistake? :D

thanksssssssss GURUDEV

I thought i was the only one confused at last but theres chaos in the comment😂😂😂😂 Plz someone help me to understand the last part

Can i design asynchronous down counter by t flip flop ?

How to pause and hold count

Great

Nice vedio

please done something with d-flip flop