this guy is saving my life each time!!!

To simplify the circuit: Use an XOR gate it will give the same output.

You could've simplified the circuit a lot more by using Qa, Qb etc as the next flip flops clock and used a 2:1 MUX to select the output between Qa and Q'a and so based upon the select input M.

The way of explaining has made understanding concepts effortless.

Learning things is far easier than the college teaching ❤️ Thank you so much neso academy for the lovely videos

1)simply use a 2:1 mux and a common mode line as combinational ckt. 2) u can't get all possible combination in M,Q,&Q(bar) table because Q & Q( bar) are always complement of each other as u using jk(1,1 state)/T ff. 3) collect the output as Qa, Qb, Qc. when M=0 u'll get up counting & when m=1 u'll get down counting (in conventional way).

Each and every topic is clear after going through ur videos...thanks

Very good and informative videos, really relieved from some of the stresss..... But, HOW IS THIS GUY USING HIS MOUSE SO SMOOTHLY???

The presentation is awesome, Thank you. Just two things, you could have used an XOR gate to avoid the mess and also you didn't point out the output.

We can simply use XOR operation (M XOR Q). Lets say, for M=1 we want to do down counting and for M=0, we have to do Up counting. Then, clock of Q1=Q0 XOR M. when M=0, clock of Q1=Q0 XOR 0=Q0(which is the condition of up counting) and when M=1, Q1=Q0 XOR 1= Q0 COMPLIMENT (which is required condition for down Counting.

Loadss of respect to neso academy n THIS PERSON , brother 🤝🤝🤝

Got in love with electronics after seeing ur videos😍

My teacher used positive and negative edge triggering randomly and the circuit design is so confusing. Thank god I saw ur playlist. It began filling in the holes that were left by my teacher.

why not just use a 2x1 MUX?...... where M will be the select line and Q and Q' will be the inputs

instead of AND-OR logic, we can simply put Ex-or gate( M and Q as inputs)

awesome videos ...tomorrow is my exam n I got so much help from the videos

Thank you so much Sir You explained really well.

I was waiting for counter video ...thanks ...

you are doing a great job thank you so much I learned a lot

شكرا @Neso Academy

another way to do this one is to use 3 xors at the outputs than 2 xors at the clocks: use output_a as (m xor Qa), output_b as (m xor Qb) and output_c as (m xor Qc) - this comes with advantage of not having clock cycle shifted by 1 (see previous video)

correction needed, q and q complement can never be same as shown in table.

You are a indeed Life saver 🙏 Thank you so much

super videos. Thanks a lot to make the subject very simple.

Superb...... That's how you teach..!! Thank you very much.

Sir u r great. Stld has been made easy only because of u.. and I recommend Ur videos to all my friends. Thank u so much for doing so good

Hello , thank you so much for this ! i was wondering though , what about the outputs , shouldnt we make a line going from Q a,b,c so we can show the result of the counting ?

We can use a multiplexer in between ever flip flop pair with Q and Q' as input and M as select line

so i built this circuit in multisim, and it turn out that when m is 0, you have a down counter (the bits ripple through to make 111 from 000 initially) and and when it's 1, you have an up counter. I made this with XOR gates instead of the AND/OR logic you implemented but the function was the same. just wanted to clarify if anyone else comes across this. Thanks for your videos, I watch all of them religiously

For an up ripple counter it knows it always increment, it only needs a signal that tells it when to. For this up/down ripple counter, it is not really ripple since it has a clk. It always change value at the posedge of clk, and it only needs to know whether to increment or decrement, which is still one signal. To design an async up/down ripple counter it needs two signals: when to change, and whether to increment or decrement. Because of setup time, constraint, it is impossible to work with only one signal. We either use delay unit which brings tons of physical requirements, or use two counters.

The use of XOR instead of AND + NOR gate (which is a 2 to 1 MUX) is logically correct. However, you need to consider loading at outputs of the flip flops, Using only Q output with XOR will have uneven loading and hence rise time will be different from fall time. This produces duty cycle != 50%. It can cause issues at higher clock frequencies.

The combinational circuit can also replace by Ex-or gate or 2:1 Mux..

Great channel!

thank you so much bro

AMAAAZINGLY described :D

terima kasih banyak

Your explanation is very good. I think we can also use also Multiplexers instead of the gates, can't we?

Can MQ'+M'Q circuit diagram with AND/OR gates be replaced with a simple XOR gate?

Sir your teaching skill is amazing !

It felt like this was rather incomplete, what was the output in this case? I am guessing if it were up counting it would be just "Y" for each bit, and " Y' " for down counting. Yet is there a way I can store a number in a counter and be able to both increment and decrement it according to my needs :D? (I feel like what you just did will do the job but still can't see it clearly) Thank you for putting all these videos for us.

dude are you like god or what . I understood the topic I felt complicated so easily

Thank you sir 🙏🏼

Thankyou very much Sir👍

YOU ARE AWESOME ! :D

We can use 2:1 mux and also exclusive or gate as a combinational ckt b/w two FF

Jazakallah Khairan

why not use a 2:1 mux in the combinational circuit part?

You can use a 2:1 mux with the select line set to M, for short

Thank You :)

Thank you sir ☺️☺️

kitna achha padathe ho aap sir

thank you very much sir

one more question :- a sequential machine produces an output 1 only when exactly two 0's are followed by 1 or exactly two 1's are followed by 0. Determine the reduced state table of the machine.

I feel using a 2:1 MUX between all pairs of consecutive flip flops would've been better, taking control input M as select line and inputs being Q and Q' of the previous flip flop and the output being fed as clock to the next flip flop.

Thanks sir

We can even use 2:1 MUX as combinational circuit instead of gates.

bro good job

Thank you very much for your video. Thanks to you I could FINALLY understand how to put both circuits together. :D

Well, actually you do not need to add Q's complement to table since it will be always opposite of Q. When you do it with only M and Q you can use just a XOR gate as combinational circuit.

Sir your chennal is best

thank you

Where is 4bit??

You could use XOR gate for making it more simple

How can Q and Q' be equal in some cases in the truth table ?

Sir, why can't we use M XOR Q. Instead of that combinational circuit

We can use multiplexer circuit with single selection line(one xor gate )

thankyou sir it is helpful

Useful even in 2023

Don't know whether it's correct or not But even 2×1 multiplexer is an alternative

This can be a good exam question.

simple xor of Qa, Qb, Qc with M as output , could make it more neater !

in the table,which you made, how can Q and Q complement have same value..e.g 1 and 1 or 0 and 0???

Just use a xor gate as y = m(xor)q that will simplify the circuit

Thanks Neso, You helped m,e apelpwelot

If you want to design this using D flip flop just connect D input to complement output , remaining same.

Design a 4-bit ripple up-down counter with two control bits C and D. The circuit counts up when the control variable C is logic ‘HIGH’ and counts down when C is logic ‘LOW’. The circuit will work only if 𝐷=1 and remains unchanged if 𝐷=0 ...????

How can Q and Q' both be zero or 1 simultaneously 3:21

for up counting we need to feed QA_bar as clk to next flop right so if it should happen at m=0 then function would be M_bar.QA_bar + M.QA . So Finally we need to use M xnor QA

What is the difference between the truth table for a synchronous counter and asynchronous counter? Or are they the same?

Sir can we use 2x1 mux instead of this combinational circuit in between?

There is a problem with this circuit, sir. If the output of the combination circuit is high when the mode is changed, the next flip flop will register that as a falling edge and change state. This design can only switch modes reliably while in the 000 state. In other words, you cannot count up 0-1-2-3 then switch modes and count down 3-2-1-0. That mode change will trigger flip flops B and C and change state, and the resulting number will be 5. This is fine, if that is the intended behavior, but you may want to disclose that.

why we not used Y=M (XOR) Q between the two flip-flops in up/down ripple counter

Hi guys, as positive feedback, I have tested your circuit, but both mode perform a down counting only. For 2 BITS counter both mode count: 11, 10, 01 and 00. I think you should revise your circuit. For 2 BITS up/down counter, please look carefully that output Q of 1st T flip-flop must trigg the clock Pulse for the second flip-flop since this is a typical of asynchronous counter. Then, the output Q and Q' of first FF must be chosen using 2 to 1 mux then we OR both and take the output of OR gate as one of it output bit itself (Verify MSB or LSB. Do the same step for the second FF, third FF and fourth FF for 4 bit up/down counter modulo 16 from 0 to 15. Thank you.

Can we use a 2×1 mux instead.. to select the required output

At 8:42, He means Qb compliment and M

This guy help me to become a Topper

Sir, can we use Xor gat directly using Q and M only?

isn't the combinational circuit used in this counter equivalent to a 2 X 1 MUX ?

U have done a mistake 5:55 in k map equation ... its :- MQ+M(BAR)Q. U have written :- M(BAR)Q + MQ(BAR)

u r great thanks

And from where we are going to consider the output

In finding the relation for Q and M why did we consider one of the inputs like 0,0,0 and 0,1,1 .I mean if we consider Q and Q' they are not supposed to be same na ?

East or West Neso is the best

Sir, I want to ask how can you list the true table that Q and Q complement have the same value?

Why not use a multiplexer with m as selector and q at I1 and ^q at I2 and take the output as the next clock?

Can we use EX-OR gate instead of 2 AND gates for the combinational circuit?

cant the combinational circuit be the 2 *1 multiplexer to select the the present state????

We can use directly ex-or gate instead of eq. of two and gates and one or gate ??

Sir, Kabhi Kabhi Lagta Hai AAP Hi Bhagvan Ho :)

bt in this case if we take q complement as a clock then q is permanently zero so from where we take output