Digital Electronics - Clocked S-R Flip-Flop
Generally, synchronous circuits change their
states only when clock pulses are present.
The operation of the basic flip-flop can be modified by including an additional input to control the behavior of the circuit.
The circuit shown above consists of two AND
gates. The clock input is connected to both of
the AND gates, resulting in LOW outputs when
the clock input is LOW. In this situation the
changes in S and R inputs will not affect the
state (0) of the flip-flop. On the other hand, if the
clock input is HIGH, the changes in S and R will
be passed over by the AND gates and they will
cause changes in the output (0) of the flip-flop
This way, any information, either 1 or 0, can be
stored in the flip-flop by applying a HIGH clock
input and be retained for any desired period of
time by applying a LOW at the clock input. This
type of flip-flop is called a clocked S-R flipflop
Such a clocked S-R flip-flop made up of two AND gates and two NOR gates.
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