Course : Systemverilog Verification 1 : L4.1: Arrays in Systemverilog

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Course : Systemverilog Verification 1 : L4.1: Arrays in Systemverilog

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5 жыл бұрын

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Пікірлер: 14

@tahirsengine 3 жыл бұрын

Awesome lecture. Lush channel.

@SystemverilogAcademy 3 жыл бұрын

Thanks for the feedback !

@bennguyen1313 2 жыл бұрын

Not sure if there's a limit on the number of dimensions that can be synthesized to run on an FPGA.. but I'm having trouble with 3D. 2D seems to work fine.. I have a 32-bit ADC, that has 16 channels.. Libero doesn't seem to have any problem synthesizing a working bitstream, that declares and accesses the array: reg [ 31 : 0 ] adcData [ 15 : 0 ]; // 16 Channels, 32 bits each reg [ 31 : 0 ] reading; adcData [ channel ] [ 31 : 0 ]

@SystemverilogAcademy 2 жыл бұрын

Hi Ben, Sorry that I can't comment more on this as I need to spend some time to check the synthesis behaviour you describe.

@alvinaug3844 3 жыл бұрын

sir, i think u have to use bit[3:0][7:0] byte;

@SystemverilogAcademy 3 жыл бұрын

You are right, at 3:06 it should have been an an array of size 3 as per the diagram, and so size should be be [3:0] not [2:0]. Thanks Alvin for this correction.

@alvinaug3844 3 жыл бұрын

@@SystemverilogAcademy thanks sir for ur great effort.Hopes u will update some lab section also with questa sim tool.It will be helpful for everybody.

@SystemverilogAcademy 3 жыл бұрын

Thanks, will try that :)

@shreemit-travelvideosin4k550 2 жыл бұрын

I also had the same doubt, hence came to comment section. Thanks Ajith Sir for the clarification.

@krishnakittu6637 4 жыл бұрын

Do more videos , helpfull

@SystemverilogAcademy 4 жыл бұрын

We will

@108ahah 3 жыл бұрын

agree! Thanks to @Systemverilog Academy

@srinivasb4955 3 жыл бұрын

Hi can you explain the packed and unpacked array in single array please

@SystemverilogAcademy 3 жыл бұрын

Hello, Not sure what exactly you are looking for. It'w common to use both packed & unpacked array declaration with a single variable. Eg: You wanted to use an array to store say 256 data packets in an array, where each packet is of 32 bit wide. The most common way to declare this array would be, logic [31:0] packet_arr[256];