FPGA #10 - Verilog == and === operators

Рет қаралды 472

5 ай бұрын

A discussion of how Verilog comparators work.
Topics:
- 0, 1, x, and z values
- ==
- !=
- ===
- !==
Related Github repo:
github.com/johnwinans/Verilog...
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#verilog

Пікірлер: 8

@vasileceteras 5 ай бұрын

This is similar to database NULL. I would name the operators 'equal' and 'is not different from' .

@jrkorman 5 ай бұрын

I remember running into these "problems" when writing a logic simulator many years back! Can make your head hurt! How many years back? I was using the "New" Turbo Pascal 5.5!

@b213videoz 4 ай бұрын

What? Turbo Pascal wouldn't be that weird 😅 And yes 5.5 was fairly advanced, it did have OOP, didn't it ?

@jrkorman 4 ай бұрын

@@b213videozTurbo Pascal wasn't weird at all. I first started using the CP/M version in 1984. Yes, Turbo Pascal 5.5 took a "swing" at OOP. What was weird was setting up the definitions of (truth tables if you will) of basic logic that included unknown values as well as how to describe pull-up/down and tri-state. No internet! No one to ask!

@barongerhardt 5 ай бұрын

In my mind it works. A normal comparison with an unknown should lead to undefined and undefined would be treated as false in most situations. The triple equals is a special operator to handle this special case. Kind of a similar situation where strings have value so they are true, but the language auto converts strings to other data types. Are the strings '0' and 'false' true or false?

@JohnsBasement 5 ай бұрын

It is like comparing a value against a NAN. Anything compared to a NAN shall be false.

@barongerhardt 5 ай бұрын

@@JohnsBasement That makes me think of the phrase "not even wrong."

@JohnsBasement 5 ай бұрын

@@barongerhardt I've been there! 😂