FPGA #13 - Verilog Always Pt. II (Nonblocking Assignments)

Рет қаралды 541

4 ай бұрын

Using the Verilog always construct with nonblocking assignments.
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Пікірлер: 9

@flexaris 4 ай бұрын

This is really excellent. Getting the details of how something like this works under the hood is so valuable for me. It really helps to give an understanding instead of someone just giving you different examples of blocking and non-blocking while explaining how you should think about them but not why they work that way. I'll certainly be following this series

@JohnsBasement 4 ай бұрын

Thanks! I'm glad to be able to help.

@DavidLatham-productiondave 4 ай бұрын

Thanks for clarifying this. I found some wierd "delayed by one clock" results on my test bench plots and now I know why. Basically, I'd only see the results of my assignments in the subsequent clock cycles. Perhaps that's how it's supposed to be. Looking forward to the techniques for handling it.

@JohnsBasement 4 ай бұрын

Yeah. That is how it is supposed to be. However, there is some leeway depending on your situation. I was just gathering around my notes for recording the next video in this series. It turns out that the background of this topic lies in the design of your Finite State Machines. Fortunately, I already have videos (and handouts) that discuss this: faculty.cs.niu.edu/~winans/CS463/2022-fa/#seq faculty.cs.niu.edu/~winans/CS463/2022-fa/#fsm You might want to put an eyeball on the 'Mealy & Moore Finite State Machines' video. I will also link then into my FPGA playlist.

@JohnsBasement 4 ай бұрын

There was a mistake in the handout that the FSM video was based on. I corrected the handout (see my course web site links in the video description) and put a note in the video. Meh... it is not too embarrassing. :-D

@captaindunsell8568 4 ай бұрын

Simulation may run multithreaded or not .. multithreaded tasks may run in a different order every run because you generally don’t control dispatch and scheduling of the underlying os

@JohnsBasement 2 ай бұрын

Yeah. If you need to control the order of handing async events, you need to do it explicitly with some sort of semaphores.

@JanEringa8k 4 ай бұрын

Dumb Question time: If the dependency chain in the active list loops A -> B -> C which affects A. Will such an infinite loop form? Or will it detect it? Or will it never form because its going to use the "old" value of the inputs and only update once its evaluated all the blocks?

@JohnsBasement 4 ай бұрын

if an always block has nothing within it that waits and it has an edge in its sensitivity list then the body runs ONCE each time an edge occurs. If its output is used back at its input (directly or indirectly) then said output will impact it on the NEXT edge... like the counters in the current example. When the loop goes across multiple always blocks then the looping of the data back around can take more than one edge. Draw up a circuit that has one endge-triggered latch for each always block. That might help. Also, note that there will be more discussion on how to use all of this coming up.