Functions and tasks in System verilog | Part 2 | Static & automatic functions |

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Күн бұрын

Declaration and initialization of functions in system verilog.
EDA code link:edaplayground.com/x/9MCw
0:00:Declaration and initialization
7:45:Static and automatic functions
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Пікірлер: 9

@prabhakarkumar8667 6 ай бұрын

Keep rising 😊

@susheelapatagar 6 ай бұрын

✌️❣️

@naveenchakali280 4 күн бұрын

mam explain how to access the automatic ,,, increment_static.count_b

@susheelapatagar 3 күн бұрын

Generally, we can't access local variables outside their function or task directly. However, if the variable is static, as explained in the video, it can be accessed. For automatic variables, hierarchical references are not allowed. To work around this, you can declare a variable in the module (outside the function/task) and assign the local automatic variable to this module-level variable inside the function/task. This way, when you need to print or use the variable outside the function/task, you can simply use that module variable.

@naveenchakali280 19 сағат бұрын

Thankyou mam

@shaikfaheed7353 19 күн бұрын

We_Lsi verify

@susheelapatagar 19 күн бұрын

+Chip verify!

@ChiragHadiya 4 ай бұрын

Ma'am Can we say automatic and dymanic is same ?

@susheelapatagar 4 ай бұрын

No their behaviour may look like same but it is not. There are actually three kinds of storage categories; static, automatic, and dynamic. Static and automatic storage are part of the declaration of a variable of any type. Automatic variables get allocated and initialized when entering a procedural scope like a task or function and they get deallocated when exiting the scope. Dynamic storage is associated with the variable’s type. You can procedurally change the size of an array, queue, or string, as well as construct a class object as any time.