This is an excellent interactive simulation and visualization!

Colin's oscilloscope picture depicting the heatmap response of a flip-flop is perfect. Depending on the technology, output delays can extend more than a clock cycle. This delay is not included in the static timing analysis used for the combinatorial logic and routing. The tools assume the designer has appropriately delt with metastability (Clock-Domain-Crossing tools or best practices).

Nice Alan Turing photo in the background!

Wow very detailed information. Thanks Matt

Definitely going to be revisiting this entire video in the future. By the way, whoever came up with the Zero To ASIC synth riff did a good job with the sound design. Always love hearing it! :)

Thank you Matt for all these good vids :)

nice Matt!

Fantastic!

You mentioned a reference book at the beginning of the video, but try as I might I can't find anything with what I'm hearing you say. Can you say which book that was?