Learned more in 20 minutes of these videos than a full month in my CMP ENG course. Life saver.

I have tried to understand JK flipflips for 15 years now and FINALLY I understand what they are, An SR latch with an extra feature ! TOGGLE. My goodness, THANK YOU !!

I dont understand .why it is getting dislikes..you are getting a great job sir..with a great teaching

I had digital electronics paper today..al I did ystrdy was watching ur videos.and im nw here typing my gratitude. thank you so much brother...you have brought satisfaction in me.cos I really feel having learned something.

u r simply amazing! i hope you get all the success u deserve

After doing a couple of hour of observation and trying different combination of gates for flip-flop I came up with these conclusions. Things get really confusing when we moved to the J-K flip flop. Let’s start from beginning, We’ve two data storing elements i.e. 1: SR NOR Latch 2: SR NAND Latch They work the same but their truth tables are completely opposite to each other. i.e. SR NOR Latch truth table S R Q 0 0 Memory state 1 0 1 0 1 0 1 1 Not used SR NAND Latch truth table S R Q 0 0 Not used 1 0 0 0 1 1 1 1 Memory state After studying these basic memory elements. We moved to SR latches with “enable”. This enable is input to the two NAND gates along with Set and Reset (as in the circuit diagram shown in video). The output of these two NAND gates is input to the Latch (SR NAND). If we replace “enable” by “Clock” we would have a flip flop. Let me ask you a question. Can’t we use any other combination of gates? Of course, we can. See the possible combinations which will work as an SR flip flop. 1. AND-NOR 2. NOR-NOR 3. OR-NAND 4. NAND-NAND (Used in video) You must be thinking what about the other combinations? 5. NAND-NOR 6. OR-NOR 7. AND-NAND 8. NOR-NAND These combinations (5 to 8) will not work as flip flop. Try making truth table for each of these combinations. After making truth table, You’ll realise that these circuits (5 to 8) are automatically going into “Invalid State” when the clock is Low/High depending upon the circuit configuration. Flip flop must follow one property, if clock goes Low or High, it must have a memory state. See these circuits are not storing data we can’t use these combinations. The only possible combinations which will work as an SR flip flop are: 1. AND-NOR 2. NOR-NOR 3. OR-NAND 4. NAND-NAND (Used in video) Hope, it cleared your doubt till now. But as we move to J-K and T flip flop. We again have some limitations. We get J-K flip flop when we feedback Q’ to the top NAND gate and Q to the bottom NAND gate Using this type of arrangement of feedback. Only two possible combinations will work i.e. 1. NOR-NOR 2. NAND-NAND Did you see? We started with 8 combinations and end up having only two useful combinations for J-K and T flip flop. If you want to use the remaining combinations for J-K and T flip flop 1. AND NOR 2. OR NAND Then, these two combinations can also be used if we make some changes in the feedback arrangement. Suppose, if we have an AND-NOR SR flip flop we want to make JK flip flop then we have to use this configuration, “If Q is input to the top AND gate and Q’ is input to the bottom AND, using this configuration the remaining two (AND-NOR, OR-NAND) will also work.” I tried every possible combination and their truth table. Everything in this video is correct and accurate. Hope it helped you!

At 2:04 we have the truth table for Sr ff with nor gate but we are using the diagram of Sr with nand gate these two totally gives different outputs

Man, i just wanna thank you for your videos, they helped me out in Varsity...i graduated last year but, Thank you so much💪💪❤

thank you so much for putting this much efforts and making it very clear and I'm really hoping that you are going to upload the the sequential circuits designing and analysis and the state digram because I have exam this week and can't find any good resources

explained....the whole concept in a very simple manner,..... thank u sir.....

for anyone having trouble remembering this, i suggest you think of it like this: Only when Q = 1, the device can be Reset, and only when Qn = 1, the device can be set. Just as a tip for remembering it more easily 😊

Thank u sir for providing such a nice explanations on the sequential circuits..it is really helpful to Me..

Man, you are awesome. I'm studying for my test and you are the only guy that I understand! thank you so much for helping me. I'll drop my PayPal contribution on your website tomorrow. keep the great work!

Wow, your presentation was really helpful! Thanks :)

Sir you are a legend. I hope you get very successful in your life!

Sir, I am very thankful to you for this.aapke lectures se Maine bahut ache marks obtained kiye.warna meri reappear thi sir electronic mein.thanks sir......

Great Explanation, one in a million! Thank you very much!

Here,T.T. for SR f/f using NOR gate and and the diagram for RS f/f using NAND gate, which is quite overwhelming if you are looking table and the diagram parallely , so nerds don't get confused 😕

First time i understood toggling. You are legendary man🙏

PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions. Your lectures are great. Thank you so much for them.

Thankuuuuuu sir You really help us alot. Clear concepts in a seconds. You really make difficult subjects easy.

Thnku so much for making this things so easy for us☺ u were a life saver to me😊

Thank you so much sir. You are simply marvelous.

That was a wonderful presentation! However, I do wanna point out that there are two main variations on the SR Latch (which are used to synthesize the JK Flip Flop)...refer to the previous video as self-evidence. WHY DOES THAT MATTER? ==>> The NOR type preserves the memory state of Q, Q_bar whenever S = R = ‘0’; S = R = ‘1’ results in the forbidden state. The NAND gate simply inverts the relationship, where all ‘0’ is forbidden and all ‘1’ is the memory preservation state. I noticed that the SR schematic is NAND based, whereas its truth table is NOR based...an alleged contradiction, if you will. I’m not a seasoned pro at this, but I think my observation makes sense, and can be used to improve the insight that you provided. Again, great video, (& to the viewers, take the presentation with a grain of salt). :) I’ll keep watching, Neso Academy. Have a great day!

Thanks sir, All your lectures are well explained. Thanks :)

"you have already studied about the SR flip-flop and D flip-flop so what is the need to study the next type of flip-flop that is your third flip-flop" YES EXACTLY WHAT I'M THINKING, WHYYYY

thanks sir. that's so better explained as compared to others

Tq sir.this videos are very usefull to me.any one cam understand ur lecturing easily. Way of teaching i loved it thanq sir

amazing job man! keep going !thanks for the help! I think you are the reason for my success !!!!!

Your lectures are very helpful.

this was grately helpful. I had a hard time understanding toggling

Thanks again and again sir for your work

THANKS A LOT, ITS JUST GOT ME READY.

I understood the concept well thank you so much sir👍

It was really helpful I apperciate your work!!!!

salute to neso academy very good explanation

Just discovered these lectures. Now I don't have to worry about my CC V

you guys are great. iam able to understand about flip flops. good job. all the best guys and thank you : )

If I assume Qn-1 = 1 and ~Qn-1 = 0, and I also set c=1, j=1 and k = 0, then the Inputs of the last nand gates (so the one for the latch) are both 0 and 1, which would result in Qn =1 and ~Qn = 1 if you go and check the network (not the truth table).

i have learned so much things from you thank youu you are the best

I wish i found this channel sooner. finals are coming up.... gonna watch a few vids to save my grade loool

Thank you so much, sir.

Congratulations 👏👏🎊 sir for 1million subscribers , keep growing

Explaination method is excellent

You are amazing. Thank you!!!

Man, you are awesome.

good clear explaination,thank you

simple to understand videos!

00:06 JK flip-flop provides an advantage over SR and D flip-flops. 00:51 Introduction to JK flip-flop 01:42 The JK flip-flop has two outputs Q and Q complement. 02:50 JK flip-flop and SR flip-flop have similar outputs except for the last case. 04:06 Analyzing the values for Q and Q complement 05:03 NAND SR latch can produce different outputs based on input changes 06:01 The JK flip-flop races between 0 and 1 06:58 JK flip flop output is the complement of the previous state.

your video is awesome.. thanks a lot

Thank you very much for uploading these videos. Now I am able to understand digital electronics a bit. But Sir, will you please do me a favour by uploading the positive and negative edge triggering of SR, D, JK and T flip flops because I am not able o understand these particular things in digital electronics. Thank You.

Great explaination sir I was totally understanded thank you for sharing this sir♥️👌

for me this tutorial is so good good job

Excellent video!

Happy teacher's day...Sir. Your videos helps me a lot. Please make video on electromagnetic.

Sir can you make a series of videos on 8085 microprocessor please!!!...and thank you for your existing content too

Hi Neso Academy, your videos are really help full, thanks for the easy explanations. for the JK flip flop i have a question, why are we considering the output of clk, S and R as Q(n+1) and why not just Q? this is causing a lot of confusion since the value iof Q and Q(n+1) are opposites. please help !!

that was rly helpful, thnx

Thank you sir for clarification toggle state

Life Saver! Thanks a lot

just awsome video tutorials....i have ever seen...@neso

appreciable...

sir in the sequential circuits playlist, you haven't added video of characteristic and excitation table of d flip flop.You directly moved onto JK flip flop. Please add it to the playlist too.

In J-k flip flop you have made use of 3 input NAND gate with 1.J 2.clk and 3 .k Until and unless we get all.3 input how will the gate work or there is previous some Q and Q bar going in 3 input NAND gate , please clarify it

thank you so much sir

awesome videos..helped a lot..thank you

It is so helpful sir.Thank u

شرح جدا واضح وبسيط .. Thank you

Is there a difference between a JK flipflop formed from an SR(using nor gates) and other SR(using NAND)?

Thank you sir🥺❤️

I have a question. Initially you had shown a S- R Flip Flop with S and R as two inputs with clock pulse present. That indicates that the NAND gates present in the first level are two input NAND gates. If this is the case then how a third input (Q or it's complement) can be added as one more input to these NAND gates? In this process the two input gates are changing to 3 input gates.

Thank you

well that's just awesome thanks

Don't you think so, that clk. Must be edge triggered (as per diagram) ?

+ Neso Academy how did u know what is the value of Q and Q' , accept the last case where u assumed

I read in book that there are 2 nand gates more with srflipflop for converting it to JK flipflop

THANK YOU

are you trying to tell me, with a JK flipflop and two high inputs, it will flipflop? Madness! PS, actually very helpful. Thankyou :)

thanks to your video, i have understood now

thank you sir

sir ,i have been hearing your voice by this tutorial ,i just i want to see your face ,your tutorials are really awesome

Thanks!!!! 🖖

Sweet voice sir😁

Amazing videos

amizing for your lecture sir

also upload video of semiconductor memory and asynchronous sequential logic

Isn't the truth table you have for the SRFF for the nor gate implementation?

Thank you very much sir🥳🥳🥳🥳

very Effective class..

Great explaination and unorthodox English ❤😅

Gracias amigo, espero poder pasar el parcial que tengo mañana

Wow great but it's modified form of Sr and d it use two inputs and invalid condition not occur also these working in a proper way actually compliment to each other

Very good videos

Thanks

Thanks brother

Sir Can you please make videos on programming of 8051 microcontroller It would help a lot of students. Thank you.

thanks sir

you took j=0 k=1 as similar to sr flipflop can you explain it on jk directly how it is coming that output ...without taking reference of sr flip flop..

so you explained the jk latch but how do we use jk latches to make JK flip flop?

His way of teaching makes me feel like... It's an offline class. Mean face to face.