What is a Master-Slave JK Flip Flop?
Master Slave JK Flip Flop is a combination of two JK flip flops which are connected in the cascaded manner
In this combination of two JK flip flop, one acts as a master flip flop and the other acts as a slave flip flop. In this master-slave flip flop, the outputs of the master JK flip flop are connected to the inputs of the slave JK flip flop. The outputs of the slave flip flop are fed back to the inputs of the master JK flip flop.
In the master-slave JK flip flop, a NOT gate (Inverter) is also used which is connected to clock signal in a manner that the inverted clock signal is applied to the slave flip flop.
Therefore, when clock signal to master flip flop is 0, then for slave flip flop the clock signal is 1, and if the clock signal to master flip flop is 1, then for the slave flip flop it 0.
Operation of Master-Slave JK Flip Flop
When the clock pulse goes to high, the slave flip flop becomes inactive and the inputs J and K can control the state of the system.
When the clock pulse goes back to low, the information is transferred from master flip flop to the slave flip flop, and the final output of the system is obtained.
From the circuit, it is clear that the master flip flop is positive level triggered and the slave flip flop is negative level triggered. Consequently, the master flip flop responds before the slave flip flop. Now, let us discuss the operation of the master-slave JK flip flop for different combinations of inputs J and K.
When J = 0 and K = 0, both JK flip flops remains inactive and hence the output Q remains unchanged. This is called Hold State of the master-slave JK flip flop.
When J = 0 and K = 1, the output Q' of the master flip flop is high and goes to the input K of the slave flip flop. The clock signal forces the slave flip flop to reset. Therefore, the slave flip flop has the same output has the master flip flop, i.e., high Q' and low Q. This is called reset state of the master-slave JK flip flop.
When J = 1 and K = 0, the output Q of the master flip flop is high and goes to the input J of the slave flip flop, the negative transition of the clock signal sets the slave flip flop. Hence, this is called the set state of the master-slave JK flip flop.
When J = 1 and K = 1, for this input combination, the master flip flop toggles on the positive transition of the clock pulse and the slave flip flop toggles on the negative transition of the clock pulse. Hence, the problem of the race around condition of the JK flip flop is solved
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