Intel joked that AMD just "glue" their chips together. Also Intel: Yep, we'll be using chiplet design soon.

And now Intel, AMD, ARM, and others are getting together to come up with an interconnect standard. We could see chiplets from different vendors on the same package. Imagine AMD cores alongside ARM and even FPGA fabric, tasked with handling different aspects of a system.

Back in the early 80's I was in a design team working on a Hardware Modeling Library at Mentor. Our device allowed 'chips' of up to 256 active pins (400 pins total) to be included into software simulations. (pre-widespread use of VHDL, obviously). I designed the physical interface into the customers' 'chip' (among other things). It was very interesting to query packaging folks from Intel, Fairchild, Wakefield, Brit-Telecom, Mercedes, etc) on what their upper-limit on pincount was... often I got a very cautious glance and ... "Well, how many can you give us?" as an answer. Many of them were only willing to talk about a more traditional hybrid-on-ceramic packaging. Whenever I turned to 3D packaging, I got a variety of answers, from "Nope, not for at least 5 years" to ... "Well, that depends on the vertical height we can have" [our device had 8 card-slots spaced 1.25 inches on center and had to account for a 0.125 inch thick controlled impedance PCB, and ZIF socketing.... either 4x64 pin, 2x 128 pin or 1x400 pin (256 active pins)]. Just for fun, I'd ask if the full 12 inches was enough. The answer would be : "Of course, yes, but we still want to have up to 8 devices installed in the card cage... and 1.25 each inches is a bit tight. " which I always interpreted as they wanted over 1 inch EACH for their concept of a 3D multi-chip interconnect including all cooling heatsinks, fans, etc. Our answer was "just pull one interface board (running 7, not 8 devices) and then you have 2.5 inches to work worth ... otherwise, buy a second HML". Some customers did not smile at that suggestion. At over 100 grand, this was not a cheap device, bitd...but you could run up to 4 boxes under one multi-unit license. Only one young engineer at an unnamed aerospace company did not flinch at the 1 inch headroom... I imagine THEY were the ones who had the most compact version of the 3D packaging at the time. BTW, this was the same set of informational "interviews" that forced us to go to 256 active pins. When we started this, we thought we could get away with "just" 128 active pins. Virtually EVERYONE told us to double it. Our engineering manager CRIED when he heard that... us design-grunts were cheering it on!! MOAR POWER is always good, right? Now, designing the backplane and send/receive data lines and phasing clocks to get insane state-transition control times, THAT was fun to do. Controlling crosstalk and race conditions in the PCB layout just about cost me my sanity, but I made it work and it remains THE QUIETEST system (as measured on a FCC testing facility at Mariposa) that I was ever associated with... and the biggest. It was an amazing box of rawk. Tho no one asked for it, getting up to 512 active pins for one model would have required a change in the way we transmitted/stored the data for vector-in, vectors-out, tri-state-data and timing analysis data.

As I understand the reverse happened when a Japanese calculator company wanted intel to make a number of different chips for their calculator industry however a person in Intel decided to combine all the functions into the first CPU chip

What is missed is that AMD chiplets DONT just WORK. They overcome the downsides of familiar MCM and revolutionize computing from the stagnant Intel sinecure it was. They have been incredibly clever. They had one shot at avoiding oblivion - they needed a single design which cost competitively scaled to ~all markets. They didnt link existing cpuS, but designed a teamable processor core unit (4 core CCX) from the ground up. as others here say, the key downside is the power & lag used by inter core data transmissions over any distance, so this was the focus of the CCX design - each of the 4 cores had a direct hardware link to each of the other (adjacent) cores - this needed only 3 such ultra fast intra ccx links on each core. inter CCX links were lavishly and liberally cached to minimise lag. Having given Fabric the optimum hardware, they then put disproportionate focus on Fabric. They initially strategically yielded to Intel on the sexy IOPS at which monolithic ~wins (gaming), & gradually gained a flanking foot hold & then advantage based on raw power and cheap costs of harvesting - even at inferior process initially. So I have a problem with dismissing it as something Intel etc. can just whip up in the lab & marketing - BS. a/ it requires a ground up re-design of their entire processor range & discarding a lot of IP b/ its been over a decade of hard yards - validation, patents, .... Infinity Fabric is a huge moat for amd - its clear that Intel were caught utterly flat footed by it in 2017 & have mostly just tried to ignore it since- not take it for the serious threat it is.

Great video! I taught a course on Advanced Packaging a number of years ago and it's nice to see the industry moving towards MCM/Chiplet designs and, now, stacking of chips. Perhaps a future video can be done on passive vs active interposers?

Computers started out with multi-chip designs. Central processing units weren't a single chip - they were several chips, all doing different functions. It was Intel's big innovation to pull all those functions together and put them onto a single piece of silicon. Not quite all (I/O and memory controllers remained external to the CPU for a long time), but close enough. The funny thing is that AMD is deliberately going backwards. They were the first to move the memory controller onto the CPU die, which provided a considerably performance boost, and now they've reversed that. You really can't stress too much how important a very high-speed interconnect is when doing such things.

MCMs faced two major issues during my time at Intel several years ago. The first was the most obvious: putting multiple chips in the same package meant the heat dissipation of the package now had to be designed for the two chips - ostensibly doubling the required heat dissipation. We handled that by throttling down the chip clocks, a process that has been largely automated by onboard temperature sensors and variable clock generators. IE., if you put two of today's advanced chips in a single package, they will self-throttle downwards. The second issue is that anytime you have a signal leave or enter a chip, it goes in or out via a pad driver, essentially an amplifier of that signal designed to drive the large capacitance of a PCB trace. This adds delay to the line. A lot of it. Internal trace drivers only have to worry about driving very short lengths of narrow and flat aluminium/copper. Not so with PCB traces. MCM pad drivers could be backed off a bit to compensate for minimal traces in the MCM, but typical MCMs unite chips that would normally be packaged separately, requiring a design change. PS., like the old movie "support your local gunslinger", keep in mind I am a stupid guy in the process world. The real process guys have to keep a fan on their heads to keep their brains from overheating :-)

I worked in the aerospace industry sometime ago. They had a MultiChip module that contained an ASIC die which they had designed in house, and dies that were basically off the shelf, Ethernet PHY, Flash, MRAM, and oscillator. MCMs have been used there for quite some time it seems. They did it because they had basically no choice.

The great thing about chiplets is the ability to mix different type of process tech on the same chiplet device. For example, the CPU (which is built on a process tuned for low capacitance) and the DRAM (which is built on a process tuned for high capacitance ...)

the infinity fabric is the secret sauce. having a suitable interconnect for the fabric is what makes this possible for sure.

Remember Pentium II? Intel had problems placing all that primary cache memory on the Processor chip, so they used the multichip approach, with the cache being the added chiplets. The cache run at half of the processor clock speed anyway. They returned to a monolithic structure with the next generation, after one year...

A funny thing about chiplets is that they're helping overall but they are so good that they leave no silicon for the low end. The low availabiliy of the 3300X and thelaco of a 5300X is becaus AMD is getting little to no chiplets with less than 6 working cores

Quick tip for you, if you use obs for recording you can set your microphone audio to be on a different audio lane than the desktop audio making it possible for you to treat the audio on an external program and then import it back during the editing process, that way you can remove the breath sounds from your audio. It can be achieved by importing the audio to audacity (First you will need to use your preferred video editor to export only the audio as an mp3 or wav for example), choosing a part of the audio where the breathing is noticeable and going to effects -> Noise Reduction -> Get Noise Profile then doing CTRL + A and going to effect -> Noise Reduction -> mess around with the settings (in your case use low settings since the breathing is noticeable but not intense) and click "ok". After that export the audio from audacity and replace the audio from the video with the exported one on your preferred video editor :)

The original Intel P6 (1995) had 2 dies, a CPU plus a wire connected cache. That's the processor I started my long verification career on. Fun times!

IBM developed the first large MCMs in the late 1970s with volume shipments starting in the 1980s. Their first MCMs have 100 and 118 chips on each module. They were originally used in mainframes.

This was so successful at the time, now Apple and Intel do it too with similar techs. good topic!

You are missing where the package innovation came from. Multi-Die packages where driven by memory and image sensor (processor). For example through silicon via technology was developed and matured for these applications. I still think that are the leading edge for this topic. A modern ISP is amazing part of technology with wafer level direct bonding, thinned image sensor chip to just 10um thickness to be ilumanted from the backside. Memory is producing stacks with up to 16 chips.

I'm surprised you didn't mention Intel tried this a few times. They did it with the Pentium 4 to get dual-cores (really dual-dies) to market. Then again with the QX6700 (2006) and Q6600's (2007) which contained two dual-core chiplets to deliver quad-core processors and they used the MCM naming for those too. There were also XEON equivalents at the time. In Intels case, AMD got to 4 cores with a single die and Intel was a bit behind so they had to use an MCM to catch up then they went back to a single die design. Now it has switched around and chiplets are being used to get higher core counts at a reduced cost like you said in the video.

Great video. I didn't really understand why chips on a bigger fab process are more expensive, but once you talked about using smaller chips to 'approximate' to the size of a bigger one, it made sense (my 'aha!' moment) - bigger fabs use more space, so there's less space to make more of them = if it has errors, it is a waste and now you've wasted all that space. If it had been made smaller, then at the least the cost for a bad chip is less. Thanks!

YES!!! I love all your videos, but I get especially excited when I see you post a tech one!

Another well presented and very informative video. Thank you.

Quick tip: Xilinx is pronounced like, "zai links."

Thanks for the overview. I have a high end threadripper CPU, nice to know how it got manufactured. First class video as usual.

Hey, could you do a video on BYD, their blade batteries and their semiconductor division?

Great topic to cover, especially given the rise of importance of substrates and interposers and inter-die interconnects

*voltage, frequency & chiplet efficiency* Multi-Chip has some very interesting EFFICIENCY options available. Since POWER DRAW does not scale linearly, and is often the limit (especially in laptops) then adding MORE chiplets at lower performance per chiplet can result in better performance. If you plan to run at a max of, say, 1500MHz you can also optimize around that as a max frequency further saving power somewhat. So there's a lot more flexibility compared to a traditional monolithic design... and not being on the most cutting edge NODE might not matter so much if you have this flexibility. Maybe put those cost savings into adding more chiplets on less efficient nodes? There's definitely going to be a BALANCE of everything that results in the best performance per dollar to make and that's going to vary depending on the product, current node costs etc.

The Ryzen chiplet design and the huge investment needed to make it work were a very risky move by AMD and almost an all in. With Bulldozer selling extremely poorly and no new cpu products on the market for about 5 years Im not sure if the AMD cpu division wouldve survived if ryzen wouldve been a failure. My guess is that it were the 2 major consoles using Bulldozer and GCN 1 keeping AMD alive. Of course we can thank the silicon gods that it workedout or wed be paying a pretty penny for Intel 4 core cpus in 14 nm to this day :D

Thanks. I was expecting more information about the packaging technology and process, that’s where the real innovation is as far as I understood. Is that covered by secrecy?

What I find fascinating is how there might be photonic interconnects on a die or between dies in the future. I generally find it really interesting, how there might be very different kind of technologies intergrated on a chip, with photonic data connects, different kinds of AI focused hardware (like Spiking Neural Networks) and traditional digital processing.

Great video! I love all of them: thanks for the great work you do! When you refer to the USB and SATA connections to the AMD Ryzen I/O chip as "analog", what about them is analog? Is it the transceiver (not sure if this is the correct term in this context) that converts the external digital USB and SATA 5v signals to the 1.2-1.5v (I believe) signals that the I/O chip uses internally?

SOC is the opposite of what amd is using. They are doing SIP system in a package, it’s been in use for decades. The next evolution of that is stacked die, where you use through silicon vias to directly connect die without bond wires and footprint increases. SOC is putting multiple die on the same wafer making large die with sub die only connected by the top metal layers or bond wires in the package. That was a large expense where board space was the primary concern. The other huge advantage to this approach is you don’t need as many different devices on a single die, reducing mask layers for each and not having to share thermal budgets at each layer. This reduces cost and complexity. The reduction in base and interconnect layers also greatly improves cost of scrap. Your net yield increases slightly but anything you scrap at end of line has man fewer masks so it costs less. These advantages are shared by Traditional SIP but stacked die is a way to take moores law into 3d and continue it beyond atomic size constraints.

Good review.

How about a video about the Inmos Transputer? Loving what you do, nice 😉

Can you do a video on yourself...how you generate so many high quality videos in such fast iterations? Truly amazing! I seriously would be interested how you do this!

Just a friendly heads up about your audio; your VO seems to have a bit of ringing to it. I noticed it around the 8:30 mark. This might be your mic arm resonating in which case it should be tightened. If the mic is desk mounted, put it on something soft so the desk can't resonate. Lastly, it might be feedback if you're listening to yourself with speakers but I'm doubtful of that last one.

Xilinx (now AMD) used a multidie approach for ultrascale too. Some designs that ran fine on V7 have problems meeting timing at the die crossing interface in ultrascale.

Around 20 years ago we saw the end of the MHz race between CPUs. Slower chips doing things smarter and more efficiently substituted for faster clock speeds. Chips have been mired in the same 'bloatware' that software finds itself.... we don't program smarter, we just throw more lines of code and billions more transistors at a problem. I believe that the 7 nM 'node' is over-extended, and just like with clock speeds, we will take a step back towards more realistic geometries. AMD has taken an interesting tack towards simplification. A database server does not need ANY graphics functionality, why include it? Design a couple of chiplets that implement database functionality in hardware, omit the graphics engine and glue them together with a CPU. Less transistors, easier geometries and better performance.

Back in the days, mainframe CPUs were basically a bunch of chiplets in a single package and a heat spreader on top. "CPU Galaxy" is a good channel to see some of these old beasts.

Large chips also have internal lag issues even at the speed of light signals that need to move 2 centimeters is always twice as long as if it needs to travel 1 cm

The Threadripper series is simply unbeatable in the prosumer market!

Credit needs to go to software developers for finding ways to parallelize tasks. All the chiplets in the world won’t work if the software isn’t designed to run on multiple cores. You young folks probably won’t remember the days before multithreaded software, but trust me when I say it sucked. Programs would freeze as they completed a task, which in the days of slow CPUs and mechanical drives was quite often.

Can you do a video on camera image sensors?

LISA SU WAS MIT SUPERSTAR IN COMPUTERS AS STUDENT. GUESS NOW DR. LISA SU.....

Thanks for this

The Brilliance of AMD is that they have - essentially - only a single 8-core CPU. By connecting many of them with different fabric chips and/or disabling broken ones by lasering them out of the circuits, they can build a chip anywhere in size from 2 CPUs to 128 CPUs - all with only 1 GPU, roughly. So AMD really makes only ONE CPU and it has 8 cores, period.

Nice vid !!!!

Remember the jump in performance that came with the Pentium II Xeon / Pro? It seemed like a big jump in performance. That used a primitive version of chiplet based L2 cache memory if I recall correctly; This is why it had a weird rectangular shape and case. I think big CPU cache is the way to go, generally.

The biggest roadblock issue for MCMs was cache memory latency bottlenecks. Consequently, integration of memory on die for CPUs GPUs and SoC would be a priority from the mid-90's onward, while on the severs side, massively parallel blade architecture solved the problems temporerally, but by ~2010, latency was again an issue. Chiplets solve this another way; splitting up the processors into manageable increments.

What about die stacking?

Mobile phone sales per year are 1.2 - 1.3 BILLION, not "in the millions each year".

Asianonetry should be a guest on MLID’s Broken Silicon podcast.

excellent - very intresting

Thank you for telling me this.

Why don't separate the systemsonachip into multiple processors like it used to be? Have separate video card and a neural AI calculator. What does "diffused" in USA mean on the AMD processor?

Intel 2 years ago, "Well, if you wanna glue 2 chips together...."

In 1983, I was at Intel and we were bonding together multiple 16k drams in a package for IBM.

Intel, 2017: "We'Re GoNnA gLuE ChIpS ToGethER" Intel, 2022: "They're called _Tiles"_

It reminds me of Intel 2 or 3 "cartrige" processsors. The reason was similar - yield issues from trying to put too much on single chip.

Maybe we can go back to having a north bridge on the motherboard in typical PCs? It would be a small step. This also reminds me of how 80286 and 80386 CPUs needed an optional “math co-processor” to be installed in the motherboard in order to perform some floating point calculations.

4:25 Dr Lisa Su is wearing a 1.5ct diamond.

@Asianometry If you could find time to make video on next generation of interconnects both data and power to deal with multi chip on a substate, the companies who are doing it and whether Intel can give competition to TSMC, Samsung with the next generation foundry, that would be awesome. When I look for information they are all fairy tales. Could you incorporate what kind of materials would be used for interconnect, interposers and why they are challenging.

I wonder whether i saw this approach with first Intel quad cores. As far as i remember these were two 2-core chips "glued together" on a single package.

The older server CPU's were split up into separate dies on the same substrate based on functionality and the needs of the customer. There were different variations for them as needed for server processing. If it needed to do more calculations it would need more cpu cores on the same substrate. Back in the 90's Intel had separate cache dies In their Pentium 2 line because they found too many failures manufacturing CPU dies with cache at the time. It really came down to the cache itself when it came to manufacturing for the reason for most of the failures. Instead of wasting a whole CPU chip just because the cache was faulty. They decided to manufacture the cache separately. It does not cost more for having more instructions on the same die size. It costs more for the higher percentage of failed chips manufactured. I.E. Bad chips = no money. It may cost more for a finer lithography process on the same die size because of the expense of the equipment and development costs and also risking higher failure rates. It may cost even more if the design of the chip may require more layers of processing. This is how AMD "Chiplets" are the idea behind their new high-end processor with their 7nm process. Very few chip manufacturers use 7nm process at this time and and it seems to be getting better but risky in the means of higher failure rates. I'm sure the failure rates are getting lower but by splitting the dies or "Chiplets" the manufacturers may create less wasted failures and earn more profit.

Agnus, Denise, and Paula would like to discuss the Amiga home computer.

I loved this video it was quite good. Could you make a more intel oriented one as for cpu’s about the tiles and explain a little 12th gen stuff and maybe what’s up and comming for intel. Maybe also for gpu currently amd and nvidia with intel hoping to get in the gpu space

You didn't mention anything about how packaging technology suddenly enables the integration of multi chiplet modules without sacrifizing the performance. And what's the difference between an SiP and a chiplet structute.

As I understand this, using ‘chiplets’ means breaking up a single chip into several components. This means that each chiplet would need extra circuitry to concentrate the signals into channels for exporting and importing data from the other chiplets. This extra channel circuitry would not be needed in a single integrated chip. That makes the integrated chip inherently more efficient that a bunch of interconnected chiplets.

I work in embedded , no such issues there :) You would have to be mad to go chiplets there. I see the point for high end designs if you want to have some scalability and lower cost with some performance drawbacks.

Also the first dual core Pentium4 and Q6600 were 2 dies glued together :)

But how are those chiplet interconnects actualy made physically? Bond wires? Solder balls?

12:03 - "Pana-see-ya" bud.

Your link to the Podcast is broken.

great coverage as always. I wonder if apple will ditch the monolithic dies for the pro lineup going forwards, they really are pushing that monolithic design SOC with their on silicon interconnect

Why do you say that first chiplet product is Epyc when AMD releases desktop Ryzen parts earlier than server?

Remember Terminator 2: judgement day? Chiplets.

10:00 "Analog functions like USB and SATA" Wtf? Can someone explain how USB is analog?

Mhm why isn't L3 a separate unit or unit group integrated with the memory controller? Also why would MCM be a curse word?

The Athlon Tri-Core was just enterprise quad-core chips that failed to yield due to manufacturing loss, so they just turned off the defective core in Microcode, sold it to consumers as the Tri-Core and we ate it up. Also because the failures were sometimes still semi-usable so we figured out ways to turn the defective CPUs back on.

A CPU you get for your computer is not SOC, not even chiplet based Ryzens. SOC includes not just the CPU and it's I/O, but also a GPU, storage and memory at least. Phones and consoles have SOCs, but not personal computers.

**Edit**: explained by a reply to my comment. 10:03 - "[...] that handles analog functions like USB and SATA [...]". Neither of those are analog, and I'm not aware of any homophone that would make that statement make sense. Did you perhaps mean something like "auxiliary"?

beter explaining SerDes, nrz, or pam 4, used on its chiplet used for data transfer on chiplet technology

And AMD's latest chiplet innovation is 3D V Cache which stacks additional cache on top of the base chiplet.

Gordon Moore understood chiplets.. in 1965 :)

Intel be like Glued together Also intel We invented tiles

I don't see Chiclets anywhere these days. Are they banned? I miss them.

Help us AMD, you're our only hope

12:03 pan-a-see-ya.

Voice synth needs a bit of a touch up. 🙂

In the 1980s AMD had the AM2900 bit-slice Microprocessor design. Do not know if anyone actually used these but they where and interesting idea, Multi-chip processor. The improvements in chip manufacturing made these redundant.

Two words, Yield!

Funny though, AMD called partition part "Tiles"

no mention of IBM mainframe MCMs

Xilinx is pronounced ZI-links, not ZEE-links. And panacea is typically pronounced with emphasis on the first and third syllables, not the second syllable. Otherwise, good video.

4:00 this is not what Moore said, because chiplets and tiles are in same package, and he said about in separately packaged. Don't give credits, when don't deserved.

superb explanation. After listening, I feel so *chipsmart*. LOL Armchair pseudo-engineer only!

Some people here in the comments confuse chiplets with MCM. They're not the same. In an MCM design a single chip can work in itself. In a chiplet design a single chip can't work in itself without an additional chip. In the case of AMD one chip (CCX) consist the cpu-cores and another chip consists the IO interfaces and connections (IO die). Neither works without the other. So a 386 motherboard or an IBM mainframe from 1965 is not based on chiplets. One thing is missing from this video: chiplets improve not just yields but the binning. Smaller chips can reach higher clockspeeds.

Why haven't we have seen any chiplet in smartphones instead of soc yet? Are they really that power hungry or is there any another issue?

do a video on the Tesla dojo thing

12:02 Hey, just so you know, that's not how you pronounce panacea [ pan-uh-see-uh ]. Those phonetic spellings aren't always super helpful. So, feel free to look it up. Most online dictionaries have audio clips for words that I often find super helpful.