Can Set Up and Hold Time be negative? | STA

Can Set Up and Hold Time be negative? | STA | Back To Basics

Рет қаралды 24,729

4 жыл бұрын

Can Set Up and Hold Time be negative? | STA | Back To Basics
Is Set up and hold time of a flip flop always positive or is it possible to have zero and negative set up and hold requirements? Watch this video to know the answer.
Some of my other videos are given below:
Set Up Time
• Set Up Time | STA | B...
Hold Time
• Hold Time | STA | Back...
D-Latch & D-Flip Flop
• D-Latch & D-Flip flop.
Find all my videos on Physical Only Cells in the following playlist.
/ @backtobasics5602
Temperature Inversion
• Temperature Inversion ...
Working of MOSFET
• Working of a MOSFET
Antenna Effects
• Antenna Effects | Phys...
Outro Template : zipansion.com/1QKOt
#SetUp#Hold#BackToBasics

Пікірлер: 32

@niroshaj.r.1730 4 жыл бұрын

Mam can u do next videos on sdc contents , static and dynamic power Dissipations please

@hakobmanukyan8233 3 жыл бұрын

You were explaining very well

@nikhilkake7931 3 жыл бұрын

I think you missed telling which one is danger either setup -ve or hold -ve. And if u given conclusion as setup -ve value is accepted but not for hold. Nice explanation, easily understand for freshers. :)

@balakrishnareddybanda5769 3 жыл бұрын

Can i get u number

@064chilukuriaditya3 3 жыл бұрын

super understood it very clearlyy

@emipushpam9417 4 жыл бұрын

Nice explanation.

@ayushsrajput301 3 жыл бұрын

Thanks a lot 😁

@subhamnayak4726 4 жыл бұрын

excellent ma'am

@rohitkumarthakur2793 4 жыл бұрын

Good explanation

@doepic8147 4 жыл бұрын

Mam please make a video on end cap cell.

@sharathreddyvancha1577 3 жыл бұрын

If clock is delayed, then the transmission gate will be turned after 5 ns and the data can be transferred only after TG is turned On and the setup time will be 3ns right, the clock delay can only cancel out delay due to Scanin combinational logic. It doesn't affect the original setup time. Correct me if I missed something

@rohitkumarthakur2793 4 жыл бұрын

Can u make video on calculation of derate

@guruprasadreddy7570 2 жыл бұрын

excellent madam👏

@jahnuchoudhury6677 4 жыл бұрын

Ma'am .. here Cp is the clock path delay for the clock of first transmission gate... and transmission gate in the loop has no clock path dalay... am I right ??

@uday5786 4 жыл бұрын

can u expain in timing analysis

@avinashvinith84 4 жыл бұрын

It was a very good explanation.

@backtobasics5602 4 жыл бұрын

Thanks :)

@sivasiitb 3 жыл бұрын

It can be 0 but not negative. Unless the clock is there how the gate opens and reach both the inverters?

@rajdeepvartak7826 Жыл бұрын

But this data combination logic is outside flip-flop then how we will consider if for negative hold flip flop?

@seelamnarendrareddy8982 4 жыл бұрын

Can you tell about sdc file

@mohangowda4282 3 жыл бұрын

hi mam , there is a typo error in last slide , it should be hold not setup for last two conditions

@ajaykodipelli8617 3 жыл бұрын

Hi Mam.. does negative and zero values of setup and hold, violates the functionality

@shashankkhope2289 5 ай бұрын

can addition of hold and setup time be negative?

@udayv1301 4 жыл бұрын

0:12 without any further delay hahaha

@sathwikpothana2184 3 жыл бұрын

How can setup time and hold time can chage they being constants?? I believe rather saying setup and hold time negative we should say hold slack and setup slack can be negative. Correct me if iam wrong.

@DalasYoo 3 жыл бұрын

I just wonder how the setup time negative related to the skew. When seeing the timing report, we always tell that the negative skew is violation. Isn't this same meaning to have setup time negative?

@pavantv749 3 жыл бұрын

I can say we get negative clock skew due to routing path of clock for the two consecutive flipflops

@KavitaSharma-wm7wq 4 жыл бұрын

How to calculate setup time for any flop .. where we can find the setup value for particular flop.?

@lokeshamara2788 4 жыл бұрын

From the lookup tables in .lib file, setup_time or hold time =f(data_transition,clock_transition)

@govindmr1984 Жыл бұрын

always we will get only setup violation but hold violations come into picture after cts ? why

@backtobasics5602 Жыл бұрын

Hold only comes into picture when the clock tree gets built, due to skew, since skew is the major cause of hold violations. Since the clock is ideal in place(skew will be 0), there won't be significant hold violations at place.