Back To Basics

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@travelfreakphani5933 4 күн бұрын

pichikeka

@ramana0070 6 күн бұрын

You have a very deep understanding of basics, this is simply an amazing explanation!!

@Narayan_BITSPilani 13 күн бұрын

Not clear

@dheerajmothukuri6158 14 күн бұрын

good oveview thank you.

@user-jg8mf3qz1g Ай бұрын

hey can you please explain the timing_report generated by tempus for STA.

@siddharthrana3106 2 ай бұрын

Excellent and very crisp explanation

@jatingupta9377 3 ай бұрын

how tapping reduces resistance?

@vinayn4767 3 ай бұрын

now i clearly understood thank mam

@noellim2062 3 ай бұрын

Very nice coaching.

@akmgowtham6445 3 ай бұрын

Great explanation ❤

@nishatt4722 4 ай бұрын

Why antenna does not occur near drain or source

@shrutichavanaik5782 4 ай бұрын

Thank you so much

@user-rm5lq1sv6f 4 ай бұрын

very good explanation, thanks.

@KarineGrigoryan-ob7gq 4 ай бұрын

I think there is mistake of connection of diode between VDD and n-well. Shouldn’t that diode connected to input instead of VDD?

@santhoshk-rw3fe 4 ай бұрын

Can we create 2 or more skew groups for a single clock ? Is it acceptable or not for better skew minimisation

@taraldc 4 ай бұрын

Very nice explanation..Very clear

@rohanyadala9096 4 ай бұрын

Very nice..

@gayathridevinarahari268 5 ай бұрын

good

@shashankkhope2289 5 ай бұрын

can setup and hold both be negative at the same same time in same ff?

@shashankkhope2289 5 ай бұрын

can addition of hold and setup time be negative?

@user-ic9ug1bz3d 5 ай бұрын

Very nice

@taraldc 5 ай бұрын

Very nice explanation..

@rinuraphy3061 6 ай бұрын

Nice explanation

@nikhilpottabathini295 6 ай бұрын

we dont have clock for latch right,, how D latch is depending on clock?

@user-on6bt1kz9m 6 ай бұрын

best explantions i ever seen

@raunakchaudhary8191 6 ай бұрын

😢pls explained practically also

@suhass4269 6 ай бұрын

Please provide clock tree structure and explain skew balancing techniques and reducing insertion delay techniques

@suhass4269 6 ай бұрын

Can you explain how the die size ie width and height are decided with an example Like take an example you have netlist with 2lacks cells and now you need to initialize a floorplan decide height and width.

@gyulanagy5910 6 ай бұрын

kzfaq.info/get/bejne/bbSTp7mglaiwY6c.html ...will be considered as forcing the logic into metastable state... this channel is not for children I guess.. Other I just understood "dewizors" is devices.

@gyulanagy5910 6 ай бұрын

kzfaq.info/get/bejne/g8CZrM5plb7DYI0.html OMG! The secret twister loop. You should learn basic electronics. Current never flows into a PNP transistor's base because that's current is in reverse direction.

@skshaheena7459 6 ай бұрын

mam really exalent expalaining mam tq u mam really before im struguling this topic mam now crearly understud mam tqu so much mam

@user-zl5jy7ie7o 6 ай бұрын

why we need to have SDC file as input in Routing stage ? tool is not considering & using at anywhere in Routing stage ?

@ganeshgani263 6 ай бұрын

I have a doubt on it ,here both npn and pnp transistor are forming but in any transistor will activate by base region ,in above you are explained with emitter and base both are in same voltages and there is no conventional current at base region then who can transistor will on

@vikasbansal4180 7 ай бұрын

Thanks a lot for all the explanations and clearing concepts in this series.

@Gangster____10 7 ай бұрын

Mam can i get this ppt

@AyushGupta29164 7 ай бұрын

mam hindi bol lo

@priyankaa6749 7 ай бұрын

Mam, Very nice explanation. Thank you for your value input

@elijahmikaelson8027 7 ай бұрын

Can you make a video on jk flip flop implementation using transmission gate

@kiranbhukya6312 7 ай бұрын

Nice explanation ma'am

@movies3946 8 ай бұрын

So, Hold check will be done at capture flop , it has to check whether data is stable after clock has reached it, whatever data that is lanched by lanched flop , after it got captured by capture flop. it should not moves so faster that it can collide with next data , it has to stable for Libray Hold time of capture flop .................... can anyone correct me ??

@Engineer884 8 ай бұрын

you said that in case of forward bias diode, the current will flow through the diode and not through the gate, but Gate current is already zero, so what's the issue??