Setup time, Hold time and Metastability | What's the origin? Can these be negative?

  Рет қаралды 5,290

Jairam Gouda

Jairam Gouda

3 жыл бұрын

Setup and Hold checks are the most essential checks in static timing analysis of modern VLSI ICs that need to be done in order to ensure the proper propagation of the data through flip-flops. These checks ensure the timing of the digital circuits without which the circuits will not function properly.
The following are the questions that I have addressed in the video:
What are setup time and hold time?
What is the origin of setup and hold time?
Can setup and hold times be negative ?
How setup and hold checks are done in VLSI?
If you liked the video, take a look at my other videos and subscribe to my channel. If you want me to cover any other topic of VLSI please mention in the comment section.

Пікірлер: 6
@DivyangaS-z4q
@DivyangaS-z4q Ай бұрын
You have mentioned the hold equation the opposite way. T(clk-q) + T(comb) > T(hold)
@kailashchandragupta8718
@kailashchandragupta8718 2 жыл бұрын
Hi, I want to know one thing.. during hold time clk is high.. and input can be passed through the transistor when clk is low. So during hold time even if data changes then also it can't reach to output because it can be passed through the transistor when clk is low
@Shivamchaudhary-xx6ci
@Shivamchaudhary-xx6ci 20 күн бұрын
Please answer this question. I also having the same doubt.
@rahulgope6044
@rahulgope6044 3 жыл бұрын
Hi sir, Could you please explain how we decide target latency and target skew for a block.
@jairamgouda
@jairamgouda 3 жыл бұрын
Hi Rahul, the target latency and skew are set by the clock design team. During Clock Tree synthesis these will be used. Clock design team reviews different types of trees that can be implemented. They use the best type for the particular type of design. There's always a trade of between skew and latency since adding additional buffers leads to insertion delay. But it's not true that always 0 skew is best. 0 skew may result in hotspot of high local IR drop. So, considering these power and reliability issues and timing issues those are set and designed.
@rahulgope6044
@rahulgope6044 3 жыл бұрын
Hi Sir, I have query regarding cts, that i have seen cts builds in nominal corner and after that optimization is happening in fast and slow corner. Why there is a preference of nominal corner over fast or slow.
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