FPGA #14 - Verilog Always Pt. III (Synthesizable Design Patterns)
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4 ай бұрынStandard Synthesizable Verilog design patterns for latches and flip-flops.
Related Github repo:
github.com/johnwinans/Verilog...
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@k3dr1 4 ай бұрын
Thank you for all the wonderful videos you keep posting, they are a great learning resource!
@JohnsBasement 4 ай бұрын
Thank you for saying! It is nice to know I can help.
@DavidLatham-productiondave 4 ай бұрын
Thanks for this. Theres a lot to unpack. I suspect ill be rewatching this one again before too long. I am always getting tripped up when a wire is needed vs a reg. Im excited about whats next.
@JohnsBasement 4 ай бұрын
Reg if it is on the left-hand-side of an assignment in an always block. Else wire.
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