This training is part 3 of 4. Closing timing can be one of the most difficult and time-consuming aspects of creating an FPGA design. The Timing Analyzer, part of the Intel® Quartus® Prime software, is an easy-to-use tool for creating Synopsys* design constraints (SDC) files and for generating detailed timing reports to shorten the process of timing closure. This part of the training explores how the Timing Analyzer fits into the overall Intel Quartus Prime software design flow. You'll learn how to incorporate your SDC files into the flow. You'll also get a more detailed look at the reporting capabilities of the tool and the types of information available in these reports.
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