Thank you for posting this. I'm trying to revive an old S100 system, and this little NOP-JP routine let me see the CPU was functioning properly with respect to reading the EPROM and executing instructions

Great video. Just today I was in the z80 peripherals datasheet trying to work out the relationship between M1 IOREQ and RD trying to wire up the PIO on my breadboard z80.

Scope out the refresh pin on halt opcode. Refresh signal can be used for CAS before RAS refresh.

The refresh line has to go low when there’s no processor activity requiring the data and address buses, I.e. instruction decode and execution. This would be when M1 is inactive, when the refresh line goes low the R register contents are put on the data bus to refresh DRAM. It is analogous to the M1 being required to access the data bus for exactly the same reason.

"i can't think of any application at all for the refresh pin" well i can, to refresh DRAM, and naively count instructions* ;) other than that the R register was abused a lot for cheap RNG seeding and stuff like that, but mostly by reading it in code. but you could totally abuse it as a 127bit counter output that tracks instructions. like hook it to a "if refresh is low and this address is on the bus, send an NMI" circuit to interrupt into some kind of debugger after a certain amount of instructions maybe. but usually there's better (e.g. M1 counting or instruction patching) ways of achieving such a thing, but if you're on a budget.... people have done video in software on those things SINCLAIR, abusing the refresh signal sounds like the least ugly application. like imagine you want some kinda multitasking scheduler to give every task their share of N (for N