LDO (Low Dropout Regulator)

Рет қаралды 75,846

Күн бұрын

Video discusses about LDO, regulator types, differences between linear and switching regulators, LDO working, both PMOS and NMOS and the differences between NMOS and PMOS LDOs.

Пікірлер: 98

@ecestories8816 3 жыл бұрын

Thanks for explaining this concept in a lucid way.

@danyalshamsi1161 2 жыл бұрын

This is really an excellent video, and channel. I can't wait to explore more of your content, sir. Thanks!

@someshprajapati4474 3 жыл бұрын

Nicely explained, focussing on the major critical design parameters.

@satishvasamsetti2399 2 жыл бұрын

Thnks for helping me to recollect all my things clearly and neat and make me confident for the interview ❤️❤️❤️

@sudhakarshrinivas 2 жыл бұрын

Thank you SIr for nice explanation. Keep posting such circuits in analog

@youngkim9799 3 жыл бұрын

The best LDO video I've ever seen.

@analoglayoutdesign2342 3 жыл бұрын

Thanks for feedback

@mukeshdas3632 2 жыл бұрын

In an open loop op-amp circuit, there is no concept of 'virtual ground'. However, in an op-amp with negative feedback such that it behaves as an amplifier, the inverting input maintains exact potential as that of the non-inverting input.

@jinyongoh Жыл бұрын

Learned a lot in short time. Thank you!

@mahadesharya6975 Ай бұрын

Excellent professor. Thanks a lot. I had watched ESD series on this channel long back

@analoglayoutdesign2342 Ай бұрын

Thanks

@JosephPMcFaddenSr 3 жыл бұрын

Thank you... good explanation even an ME like me can understand

@Arturochirinoscruz Жыл бұрын

Excelente 👌 explicación 👍 gracias ingeniero.

@analoglayoutdesign2342 Жыл бұрын

Thanks for the feedback

@kotresh18 3 жыл бұрын

Thank you sir, nice explanation

@akshayjabi3090 3 жыл бұрын

Good Explanation Sir :)

@maherkudle8439 4 ай бұрын

Clear explanation .Thank you ❤

@analoglayoutdesign2342 4 ай бұрын

You're welcome 😊

@asha503 3 жыл бұрын

Nicely explained 👍👍

@josephbuganski8066 3 жыл бұрын

agreed, good job

@sukantachanda7491 3 жыл бұрын

Nice explain sir.many many thanks sir👌👌👌👌👌👌👌👌👌👌👌👌👌👌

@dundu007 3 жыл бұрын

Very nicely explained..

@sevakantonyan9833 3 жыл бұрын

Great content,

@analoglayoutdesign2342 3 жыл бұрын

Thanks for the feedback

@ivkreddy8 3 жыл бұрын

Superb sir

@skn3789 2 жыл бұрын

When we get oscillations at the output of the LDO what is suggested to be changed first and subsequently from layout perspective?

@analoglayoutdesign2342 2 жыл бұрын

So if I understand properly, there are no oscillations in schematic simulations but after layout and parasitic extraction you are facing stability issues.. It's very difficult to point out without knowing more about ldo: architecture, current, compensation etc..

@bipashanath8697 2 жыл бұрын

The best video 👏

@analoglayoutdesign2342 2 жыл бұрын

Thanks for feedback

@srikanthSrikanth-to7jh 3 жыл бұрын

1 St view Thanks a lot sir

@deepikasharma-gn4hn 2 жыл бұрын

Very good information and excellent presentation style. I have one query... How do choose the specifications of the error amplifier? I mean how to budget the bandwidth and gain for the error amplifier?

@analoglayoutdesign2342 2 жыл бұрын

Error amplifier gain is calculated based on your output voltage accuracy reqd. Bandwidth requirements of the amplifier depends on overall stability of the LDO and response time of the LDO..hope this helps

@rajathmvenugopal8313 3 жыл бұрын

Great video sir, i had one doubt , in nmos LDO when vref and feedback voltage is same the output of opamp becomes 0 and vgs is either 0 or -ve depending on the predefined voltage at output. So will there be any offset output voltage added just to turn on the NMOS. Correct me if i went wrong anywhere.

@analoglayoutdesign2342 3 жыл бұрын

in NMOS LDO when vref and vout are same; 1. resistor divider is not required. 2. The output of the opamp should be greater than output voltage by one Vth. suppose, Vout=1.25V, (equal to Vref), then the output of Opamp should be Vout+Vth of NMOS; i.e. 1.25+1V (assuming Vth of NMOS=1V). Hope this clarifies.

@rajathmvenugopal8313 3 жыл бұрын

@@analoglayoutdesign2342 ,thanks sir that was very insightful. Sorry for the bad format of question formation. My question being reiterate 1)when vref=vfedback (considering virtual short) the opamp output to gate of nmos would be 0. Since for nmos vgs to be positive , won't the nmos be turned off?.

@analoglayoutdesign2342 3 жыл бұрын

Ok if vref and vout are equal, then a.c or small signal output of opamp will be zero. But large signal or DC levels will still be maintained by opamp output. Hope I answered.

@rajathmvenugopal8313 3 жыл бұрын

@@analoglayoutdesign2342 , great sir , yeah it's clarified now

@pravinsengottaiyan9244 2 жыл бұрын

I am looking more videos from you..........

@avis6471 Жыл бұрын

so helpful tnx

@analoglayoutdesign2342 Жыл бұрын

Thanks for feedback

@sutejtorvi9946 3 жыл бұрын

Hi sir. I have two questions. 1) How do you calculate the W/L ratio accurately of Pmos pass fet for a specific load current. 2) What is the main contributor to set the output voltage, error amplifier or resistor divider?

@analoglayoutdesign2342 3 жыл бұрын

1. Decide whether you need passfet in saturation or linear. Generally saturation so that we get gain. Keep L min. Now u know current, vds, kp... So calculation is straight fw... 2. U can use both. When you change the reference voltage, output voltage will change accordingly. The error amp should have that input voltage dynamic range. But to get voltage reference which varies linearly is difficult. Resistor divider should have resistor bank to program the output voltage. Here the quiescent current will change when feedback resistor value changes. Hope its clear..

@sutejtorvi9946 3 жыл бұрын

@@analoglayoutdesign2342 Ok sir. Thank you.

@SigitYuwono 2 жыл бұрын

Note: 05:30 classification PS: linear switching

@analoglayoutdesign2342 2 жыл бұрын

Are you referring to hybrid LDO?

@pavankori6986 Жыл бұрын

Nice explain

@analoglayoutdesign2342 Жыл бұрын

Thanks

@binhho7816 Жыл бұрын

Hello sir, In nMOS LDO case i have some concerns that i have learned that nMOS works in saturation mode when Vds>Vgs-Vt. In your example, Vds=3.3-2.5>3.5-2.5-1. It seems like LDO still works with Vdd=3.3 in case Vg is not greater than 4.3. If I have any mistake, please correct me.

@analoglayoutdesign2342 Жыл бұрын

In NMOS LdO, NMOS stage is in common drain configuration. Let’s say vin=3.3, vout=2.5 and Vt=1v , then gate voltage should be vout+vt at least I.e. 2.5+1=3.5 Question now is where do I get 3.5v which is higher than supply of 3.3v…vin and Vdd are same…

@analoglayoutdesign2342 Жыл бұрын

Hope this answers your question

@erfanali5888 3 жыл бұрын

Very nice talk, do you share your slides as well? Are they downloadable ?

@analoglayoutdesign2342 3 жыл бұрын

Hi, in the slides I will not put in full information. I will write on it and explain. So please go thru the video by pausing wherever required and my suggestion is to make some notes. This is what I do when I listen to lectures. That way it will be very useful. For downloadable material, there is quite a lot of material and app notes from all product companies. That will also help.

@analoglayoutdesign2342 3 жыл бұрын

Thanks for the feedback. If you have further questions, please post it in the comments section. Thanks

@pruthvimuchharla5525 2 жыл бұрын

How do we derive Transfer function from VDD to VOUT?

@analoglayoutdesign2342 2 жыл бұрын

Basically for psrr, we will do this. We need to write down small signal equivalent ckt for that and then get the transfer function

@manharm494 3 жыл бұрын

Hi sir... Waiting for few more

@analoglayoutdesign2342 3 жыл бұрын

Sure..

@saikrishna1640 2 жыл бұрын

How the output voltage decreases when the load current increases suddenly

@saikrishna1640 2 жыл бұрын

Pls explain this.

@analoglayoutdesign2342 2 жыл бұрын

When the current increases suddenly, the pass element cannot provide so much current. Current is provided by load capacitor. When charge(current) is removed from Capacitor, it's voltage reduces.. which is nothing but output voltage... hope this answers

@saikrishna1640 2 жыл бұрын

Understood, Thanks!!

@sajnak2704 3 жыл бұрын

Sir,Can you a video on pole zero compensation . There is no video telling practical approach on this topic anywhere.

@analoglayoutdesign2342 3 жыл бұрын

Ok. Will upload one video on ldo compensation

@someshprajapati4474 3 жыл бұрын

@@analoglayoutdesign2342 yes sir, it would help greatly.

@AnalogABC 2 жыл бұрын

In dropout voltage why value is =0.3?

@analoglayoutdesign2342 2 жыл бұрын

Need not be 0.3... can be even 0.1v ...I just took an example of 0.3v

@bindumadhavi3928 2 жыл бұрын

why load cap is needed in ldo? what is purpose of that load cap in ldo?

@analoglayoutdesign2342 2 жыл бұрын

Load cap supplies instantaneous load currents. Otherwise the transient load regulation will be very bad.

@bindumadhavi3928 Жыл бұрын

@@analoglayoutdesign2342 thank you

@vectorhehe7905 2 жыл бұрын

Hello sir, thanks for the great video. Got 2 questions: 1. if Vin-Vout = V drop_out, at 35:43, V drop_out is 10-3.3=6.7V, then how come the drop out voltage is 3.6V, and later it becomes 3.6-3.3=0.3V? which one is the real drop out voltage? 2. Why when Vin is under 3.6V, the error amp won't work? Looking forward for the reply. Thank you

@analoglayoutdesign2342 2 жыл бұрын

Drop out voltage is the minimum voltage between Vin and vout after which regulation stops.

@analoglayoutdesign2342 2 жыл бұрын

Regulation stops bcos the Vin and vout difference is so less that pass element becomes a simple series resistor between Vin and vout

@vectorhehe7905 2 жыл бұрын

@@analoglayoutdesign2342 Thank you sir, you mean the pass element is similar to diode connection?

@jayateerthar5224 2 жыл бұрын

@@vectorhehe7905 no.. it's not like diode connected..it's in linear region..simple mos resistor

@vectorhehe7905 2 жыл бұрын

@@jayateerthar5224 oh you are right, I forgot this pass element here is a PMOS

@skzfam1008 2 жыл бұрын

Hi,why we connect loads in circuits

@analoglayoutdesign2342 2 жыл бұрын

LDO is a power supply. It can supply current to different circuits that load the power supply. Load means load current.

@w43o21l2f 3 жыл бұрын

We have some design ideas, Sir. Would it be possible and appropriate to hire you as our advisor? How can we connect?

@analoglayoutdesign2342 3 жыл бұрын

Please email me your contact details jt.analog@gmail.com

@sushantsharma180 2 жыл бұрын

But giving 5 voltage and having 2.5 voltage, There will be a so much drop using NMOS pass element

@analoglayoutdesign2342 2 жыл бұрын

That’s true. NMOS pass element when used with lesser difference between Vin and Vout, they use a charge pump to boost the supply of the amplifier driving the pass element.