This training is part 4 of 4. Closing timing can be one of the most difficult and time-consuming aspects of FPGA design. The Timing Analyzer, part of the Intel® Quartus® Prime software, is an easy-to-use tool for creating Synopsys* design constraints (SDC) files and generating detailed timing reports to shorten this timing closure process. This final part of the training discusses the SDC constraints required to fully constrain a design. You'll learn how to constrain clock and I/O paths, the minimum constraints required for the tool to consider a design to be fully constrained. You'll also learn how to adjust how a timing analysis is performed through the use of clock latency, uncertainty and timing exceptions.
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