You are the best!!!! Thank you so much. I understood how to link the PS and PL. I did in my Cora Z7 board.

Excellent presentation. The diagram in the beginning was really helpful to illustrate the process flow. Keep up the good work, this is very valuable for the uninitiated.

*Summary* - Stacey is continuing her Zinc series on KZfaq; this is part three. - The video focuses on adding custom logic to a Vivado block diagram. - The current block diagram has wrapper files that forward internal signals. - Stacey plans to add her own top-level code to include both modules (existing and new). - She walks through the process of creating external and internal signals. - External signals are for communication with the outside world. - Internal signals are for interfacing with the existing block diagram. - She also sets up clock and reset signals, specifying that the clock is supplied by a processor already in the block diagram. - Stacey modifies a block RAM port to create a dual port RAM. - She has pre-written code that she adds to the project, specifically for generating Fibonacci numbers. - This code writes a new Fibonacci number to block RAM every half a second. - After adding the code, Stacey exports the hardware and switches to Vitis. - In Vitis, she updates the hardware specification and rebuilds the application. - She tests the existing code on her hardware to confirm it still works. - Stacey then modifies her code to read from the block RAM every second and expects to see new Fibonacci numbers in her debug output. The video serves as a comprehensive guide for adding custom logic to an FPGA project using AMD Vivado and AMD Vitis. It covers creating signals, updating hardware specifications, and modifying code.

Hey Stacey, thanks much for your Zynq series. If you could go on with an AXI stream slave interface - e.g. for reading data from an ADC - that would be terrific! Thanks again for the superb YT videos. Regards from Germany, Frank

Nice overview - this really helps, thank you so much for putting these videos out there.

I appreciate your thorough and indepth tutorials for such a niche subject. I really enjoy FPGA and HDL but unfortunately it's quite hard to have a hobby in such a niche field without working in it.

LOLZ I wish I had seen this sooner. I switched from an inferred BRAM of some struct to the block diagram BRAM, and my addressing seemed weird. First hint was the BRAM had a 4 bit write enable port and 32 bit address, but it took me 30 minutes to work out the BRAM wanted a byte address and not a word index. Seeing your excellent videos would have saved me a tonne of time Also, thanks for the intro to the board tab. No idea how I missed it before

Really instructive videos

Thank you!! It's really helpful!

It's really helpful for beginner like me. Have you implement that neural network on fpga. Thanks

Can you help me create axi transactions to write to fpga. I have everything ready. I connect clocking wizard, processor system reset, jtag axi, and my own ip core. When I run simulation everything is working fine. Also when I send write transactions it confirms the write data but when I read my data it reads zeros and not the result I expect.

Can you do a tutorial about how to use TCP communication to transfer data in Zynq ?? Pleasee

Thank you very much for the helpful video. Please, I have a question; I have ZYBO_7Z010CLG400 board, I use its BRAM to save 8100 Byte (byte width). The report of resources utilzation is: 60 available 8 used 13.33 % I dont understand what (8 used) mean? I want to save more than 8100 byte but I cant.

Hello Stacey , can you do a part 4 where you will try to use linux project in vitis instead of standalone project?

thanks for sharing, my program build fine, But it does not show the text, data, bss ,dec values, so I can not see my elf size! what's missing there?

First thing first , this channel is awesome.......... I just want to know about the FPGA because need to design ( just design) a CPU and my own game console. and where to start my CPU design journey?

can you suggest me that, to which pin the external clock source of my created block design is to be connected in zc706 board ..?

Please, make video tutorial about Static Time Analysis in Vivado

Hi, great videos. I did the fibonacci project. And I see the number changes once per second. In your example, it's twice per second. When I check Vivado project, I see that FCLK is set to 50 MHz and in fibonacci verilog, I see localparam CLK_MHZ = 100; ==> Is that the root cause of my problem? It should be CLK_MHZ = 50 ?

hello maam, can you please make a video of how to use qspi ip in vivado to connect external adc

Id like a one on one tutorial. Possible?

promo sm 😆